| /third_party/openh264/codec/common/arm64/ |
| D | expand_picture_aarch64_neon.S | 64 msub x5, x5, x1, x0
116 msub x5, x5, x1, x0
135 msub x5, x5, x1, x0
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| /third_party/node/deps/v8/src/compiler/ |
| D | machine-operator-reducer.cc | 356 Int64BinopMatcher msub(m.left().node()); in Reduce() local
357 node->ReplaceInput(0, msub.left().node()); in Reduce()
358 node->ReplaceInput(1, msub.right().node()); in Reduce()
1966 Int32BinopMatcher msub(sub); in TryMatchWord32Ror() local
1967 if (!msub.left().Is(32) || msub.right().node() != y) return NoChange(); in TryMatchWord32Ror()
2060 Int32BinopMatcher msub(m.left().node()); in ReduceWord32Equal() local
2061 node->ReplaceInput(0, msub.left().node()); in ReduceWord32Equal()
2062 node->ReplaceInput(1, msub.right().node()); in ReduceWord32Equal()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrFPU.td | 200 def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
211 def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,
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| D | MipsInstrFPU.td | 654 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
659 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
665 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
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| D | MipsScheduleGeneric.td | 807 // abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s
822 // madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw],
918 // cvt.?.?, ceil.?, floor.?, round.?, trunc.? (n)madd.? (n)msub.?
1575 // madd?.q.[hw], msub?.q.[hw], mul?.q.[hw]
|
| D | MipsScheduleP5600.td | 506 // madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds],
512 // madd.ps, msub.ps, nmadd.ps, nmsub.ps
|
| D | MicroMipsDSPInstrInfo.td | 43 class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>;
|
| D | MipsDSPInstrInfo.td | 816 class MSUB_DSP_DESC : MADD_DESC_BASE<"msub", MipsMSub, NoItinerary>;
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| D | MicroMipsInstrInfo.td | 930 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
|
| /third_party/skia/third_party/externals/icu/source/i18n/ |
| D | decNumber.cpp | 824 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberAnd() local
842 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberAnd()
849 if (ub>msub) b=0; in uprv_decNumberAnd()
1840 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberOr() local
1857 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberOr()
1864 if (ub>msub) b=0; in uprv_decNumberOr()
3270 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberXor() local
3287 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberXor()
3294 if (ub>msub) b=0; in uprv_decNumberXor()
|
| /third_party/icu/icu4c/source/i18n/ |
| D | decNumber.cpp | 824 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberAnd() local
842 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberAnd()
849 if (ub>msub) b=0; in uprv_decNumberAnd()
1840 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberOr() local
1857 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberOr()
1864 if (ub>msub) b=0; in uprv_decNumberOr()
3270 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberXor() local
3287 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberXor()
3294 if (ub>msub) b=0; in uprv_decNumberXor()
|
| /third_party/node/deps/icu-small/source/i18n/ |
| D | decNumber.cpp | 824 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberAnd() local
842 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberAnd()
849 if (ub>msub) b=0; in uprv_decNumberAnd()
1840 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberOr() local
1857 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberOr()
1864 if (ub>msub) b=0; in uprv_decNumberOr()
3270 const Unit *msua, *msub; /* -> operand msus */ in uprv_decNumberXor() local
3287 msub=ub+D2U(rhs->digits)-1; /* -> msu of rhs */ in uprv_decNumberXor()
3294 if (ub>msub) b=0; in uprv_decNumberXor()
|
| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | vp9mc_neon.S | 527 msub x0, x1, x4, x0
529 msub x2, x3, x4, x2
|
| D | vp9mc_16bpp_neon.S | 506 msub x0, x1, x4, x0
508 msub x2, x3, x4, x2
|
| /third_party/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 469 TEST(msub) { in TEST() argument
472 COMPARE(msub(w0, w1, w2, w3), "msub w0, w1, w2, w3"); in TEST()
473 COMPARE(msub(w30, w21, w22, w16), "msub w30, w21, w22, w16"); in TEST()
474 COMPARE(msub(x0, x1, x2, x3), "msub x0, x1, x2, x3"); in TEST()
475 COMPARE(msub(x30, x21, x22, x16), "msub x30, x21, x22, x16"); in TEST()
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| D | test-trace-aarch64.cc | 251 __ msub(w22, w23, w24, w25); in GenerateTestSequenceBase() local
252 __ msub(x26, x27, x28, x29); in GenerateTestSequenceBase() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 5051 "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006"
5052 "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q"
7128 …{ 6568 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_…
7129 …{ 6568 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMi…
7130 …{ 6568 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__…
7131 …{ 6568 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie…
7132 …{ 6573 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__A…
7133 …{ 6573 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2…
7134 …{ 6573 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR6…
7135 …{ 6580 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32A…
[all …]
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| /third_party/node/deps/v8/src/compiler/backend/arm64/ |
| D | instruction-selector-arm64.cc | 2475 Int32BinopMatcher msub(sub); in VisitWord32Compare() local
2476 if (msub.left().Is(0)) { in VisitWord32Compare()
2478 node->ReplaceInput(1, msub.right().node()); in VisitWord32Compare()
2487 if (can_cover) sub->ReplaceInput(1, msub.left().node()); in VisitWord32Compare()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | macro-assembler-arm64-inl.h | 836 msub(rd, rn, rm, ra); in Msub()
|
| D | assembler-arm64.h | 744 void msub(const Register& rd, const Register& rn, const Register& rm,
|
| /third_party/skia/third_party/externals/icu/source/data/unit/ |
| D | tr.txt | 2536 dnam{"msub"}
|
| /third_party/icu/icu4c/source/data/unit/ |
| D | tr.txt | 2632 dnam{"msub"}
|
| /third_party/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 195 0x~~~~~~~~~~~~~~~~ 1b18e6f6 msub w22, w23, w24, w25
196 0x~~~~~~~~~~~~~~~~ 9b1cf77a msub x26, x27, x28, x29
|
| D | log-disasm | 195 0x~~~~~~~~~~~~~~~~ 1b18e6f6 msub w22, w23, w24, w25
196 0x~~~~~~~~~~~~~~~~ 9b1cf77a msub x26, x27, x28, x29
|
| D | log-cpufeatures-custom | 195 0x~~~~~~~~~~~~~~~~ 1b18e6f6 msub w22, w23, w24, w25
196 0x~~~~~~~~~~~~~~~~ 9b1cf77a msub x26, x27, x28, x29
|