| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrFormats.td | 113 bits<6> op3;
117 let Inst{24-19} = op3;
130 let op3 = op3val;
149 let op3 = op3val;
162 let op3 = op3val;
175 let op3 = op3val;
189 let op3 = op3val;
203 let op3 = op3val;
218 let op3 = op3val;
239 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
[all …]
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| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/spirv_assembly/ |
| D | vktSpvAsmTrinaryMinMaxTests.cpp | 127 T min3(T op1, T op2, T op3) in min3() argument
129 return std::min({op1, op2, op3}); in min3()
133 T max3(T op1, T op2, T op3) in max3() argument
135 return std::max({op1, op2, op3}); in max3()
139 T mid3(T op1, T op2, T op3) in mid3() argument
141 std::array<T, 3> aux{{op1, op2, op3}}; in mid3()
358 char* op3 = inputByte + m_operandSize * 2u; in calculateResult() local
366 reinterpret_cast<void*>(op3)); in calculateResult()
371 op3 += m_componentSize; in calculateResult()
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| /third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/spirv_assembly/ |
| D | vktSpvAsmTrinaryMinMaxTests.cpp | 127 T min3(T op1, T op2, T op3) in min3() argument
129 return std::min({op1, op2, op3}); in min3()
133 T max3(T op1, T op2, T op3) in max3() argument
135 return std::max({op1, op2, op3}); in max3()
139 T mid3(T op1, T op2, T op3) in mid3() argument
141 std::array<T, 3> aux{{op1, op2, op3}}; in mid3()
358 char* op3 = inputByte + m_operandSize * 2u; in calculateResult() local
366 reinterpret_cast<void*>(op3)); in calculateResult()
371 op3 += m_componentSize; in calculateResult()
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| /third_party/spirv-tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/skia/third_party/externals/spirv-tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/ |
| D | amd_ext_to_khr.cpp | 77 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMinMax() local
87 new_operands.push_back({SPV_OPERAND_TYPE_ID, {op3}}); in ReplaceTrinaryMinMax()
114 uint32_t op3 = inst->GetSingleWordInOperand(4); in ReplaceTrinaryMid() local
118 {op2, op3}); in ReplaceTrinaryMid()
121 {op2, op3}); in ReplaceTrinaryMid()
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| /third_party/cmsis/CMSIS/Core/Include/a-profile/ |
| D | cmsis_armclang_a.h | 502 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
506 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| D | cmsis_clang_a.h | 712 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
716 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| D | cmsis_gcc_a.h | 735 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
739 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| /third_party/ffmpeg/libavcodec/ppc/ |
| D | me_cmp.c | 444 register vector signed short op3 = vec_perm(but2, but2, perm3); \ in hadamard8_diff8x8_altivec()
445 res = vec_mladd(but2, vprod3, op3); \ in hadamard8_diff8x8_altivec()
612 register vector signed short op3 __asm__ ("v29") = \ in hadamard8_diff16x8_altivec()
616 res1 = vec_mladd(but2, vprod3, op3); \ in hadamard8_diff16x8_altivec()
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| /third_party/node/deps/v8/src/diagnostics/arm/ |
| D | disasm-arm.cc | 1906 int op3 = instr->Bit(6); in DecodeFloatingPointDataProcessing() local
1907 if (((op0 & 0b1000) == 0) && op2 && !op3) { in DecodeFloatingPointDataProcessing()
1959 } else if (instr->Opc1Value() == 0x7 && (op1 >> 3) && op2 && op3) { in DecodeFloatingPointDataProcessing()
2240 int op3 = instr->Bit(6); in DecodeAdvancedSIMDTwoOrThreeRegisters() local
2389 } else if (op1 != 0b11 && !op3) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
2400 } else if (op1 != 0b11 && op3) { in DecodeAdvancedSIMDTwoOrThreeRegisters()
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| /third_party/cmsis/CMSIS/Core/Include/m-profile/ |
| D | cmsis_tiarmclang_m.h | 1439 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1443 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| D | cmsis_clang_m.h | 1453 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1457 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| D | cmsis_armclang_m.h | 1452 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1456 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| D | cmsis_gcc_m.h | 1674 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) in __SMMLA() argument
1678 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()
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| /third_party/libdrm/freedreno/kgsl/ |
| D | msm_kgsl.h | 383 unsigned int op3; member
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_nir_lower_tess_io.cpp | 104 r600_umad_24(nir_builder *b, nir_ssa_def *op1, nir_ssa_def *op2, nir_ssa_def *op3) in r600_umad_24() argument
106 return nir_build_alu(b, nir_op_umad24, op1, op2, op3, NULL); in r600_umad_24()
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| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-arm64.h | 2495 T FPProcessNaNs3(T op1, T op2, T op3) { in FPProcessNaNs3() argument
2500 } else if (IsSignallingNaN(op3)) { in FPProcessNaNs3()
2501 return FPProcessNaN(op3); in FPProcessNaNs3()
2508 } else if (std::isnan(op3)) { in FPProcessNaNs3()
2509 DCHECK(IsQuietNaN(op3)); in FPProcessNaNs3()
2510 return FPProcessNaN(op3); in FPProcessNaNs3()
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| /third_party/json/tests/src/ |
| D | unit-json_patch.cpp | 29 json op3 = R"({ "value": "foo", "path": "/a/b/c", "op": "add" })"_json; variable
33 CHECK(op1 == op3);
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| /third_party/skia/third_party/externals/spirv-cross/ |
| D | spirv_glsl.hpp | 632 uint32_t op3, const char *op);
652 uint32_t op3, const char *op, SPIRType::BaseType offset_count_type);
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| /third_party/mesa3d/src/freedreno/vulkan/ |
| D | msm_kgsl.h | 685 unsigned int op3; member
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| /third_party/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 4827 T FPProcessNaNs3(T op1, T op2, T op3) {
4832 } else if (IsSignallingNaN(op3)) {
4833 return FPProcessNaN(op3);
4840 } else if (IsNaN(op3)) {
4841 VIXL_ASSERT(IsQuietNaN(op3));
4842 return FPProcessNaN(op3);
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| /third_party/mesa3d/src/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 2640 Value *op3[2] = { NULL, NULL }; in split64MulMad() local
2643 bld.mkSplit(op3, 4, i->getSrc(2)); in split64MulMad()
2645 op3[0] = i->getSrc(2); in split64MulMad()
2646 op3[1] = zero; in split64MulMad()
2652 bld.mkOp3(OP_MAD, hTy, tmpRes1Hi, op1[1], op2[0], op3[1]); in split64MulMad()
2664 bld.mkOp3(OP_MAD, hTy, def[0], op1[0], op2[0], op3[0])->setFlagsDef(1, carry); in split64MulMad()
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | hevcdsp_idct_neon.S | 400 .macro add_member in, t0, t1, t2, t3, t4, t5, t6, t7, op0, op1, op2, op3, op4, op5, op6, op7, p
404 sum_sub v24.4s, \in, \t3, \op3, \p
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| /third_party/mesa3d/src/compiler/glsl/ |
| D | ir.cpp | 188 ir_rvalue *op2, ir_rvalue *op3) in ir_expression() argument
196 this->operands[3] = op3; in ir_expression()
|