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Searched refs:qword (Results 1 – 25 of 38) sorted by relevance

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/third_party/lame/libmp3lame/i386/
Dscalar.nas538 pmov mm0,qword [eax]
539 pmov mm1,qword [eax+8]
540 pfmul mm0,qword [edx]
541 pfmul mm1,qword [edx+8]
544 pmov qword [sp(%$p)],mm0
557 pmov mm0,qword [eax]
558 pmov mm1,qword [eax+8]
559 pfmul mm0,qword [edx]
560 pfmul mm1,qword [edx+8]
562 pmov mm2,qword [eax+16]
[all …]
/third_party/skia/third_party/externals/swiftshader/src/Shader/
DConstants.hpp42 qword maskQ0Q[16];
43 qword maskQ1Q[16];
44 qword maskQ2Q[16];
45 qword maskQ3Q[16];
46 qword invMaskQ0Q[16];
47 qword invMaskQ1Q[16];
48 qword invMaskQ2Q[16];
49 qword invMaskQ3Q[16];
/third_party/skia/third_party/externals/swiftshader/src/Pipeline/
DConstants.hpp44 qword maskQ0Q[16];
45 qword maskQ1Q[16];
46 qword maskQ2Q[16];
47 qword maskQ3Q[16];
48 qword invMaskQ0Q[16];
49 qword invMaskQ1Q[16];
50 qword invMaskQ2Q[16];
51 qword invMaskQ3Q[16];
/third_party/vulkan-loader/loader/
Dunknown_ext_chain_masm.asm38 …mov rax, qword ptr [rcx] ; Dereference the wrapped VkPhysicalDevice…
39 …mov rcx, qword ptr [rcx + PHYS_DEV_OFFSET_PHYS_DEV_TRAMP] ; Load the unwrapped VkPhysicalDev…
40 …jmp qword ptr [rax + (PHYS_DEV_OFFSET_INST_DISPATCH + (PTR_SIZE * num))] ; Jump to the next fu…
46 …mov rax, qword ptr [rcx + ICD_TERM_OFFSET_PHYS_DEV_TERM] ; Store the loader_icd…
47 …cmp qword ptr [rax + (DISPATCH_OFFSET_ICD_TERM + (PTR_SIZE * num))], 0 ; Check if the next fu…
49 …mov rcx, qword ptr [rcx + PHYS_DEV_OFFSET_PHYS_DEV_TERM] ; Load the unwrapped V…
50 …jmp qword ptr [rax + (DISPATCH_OFFSET_ICD_TERM + (PTR_SIZE * num))] ; Jump to the next fun…
53 …mov rcx, qword ptr [rax + INSTANCE_OFFSET_ICD_TERM] ; Load the loader_inst…
54 …mov rax, qword ptr [rcx + (FUNCTION_OFFSET_INSTANCE + (CHAR_PTR_SIZE * num))] ; Load the func …
57 …mov qword ptr [rsp + 32], rax ; Move the func name o…
[all …]
/third_party/skia/third_party/externals/swiftshader/src/Renderer/
DSurface.hpp365 typedef uint64_t qword; typedef in sw::Surface
376 qword a;
393 qword alut; // Skip first 16 bit
411 qword ylut; // Skip first 16 bit
422 qword xlut; // Skip first 16 bit
436 qword rlut; // Skip first 16 bit
/third_party/libdrm/radeon/
Dradeon_cs.h123 static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) in radeon_cs_write_qword() argument
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t)); in radeon_cs_write_qword()
/third_party/mesa3d/src/panfrost/midgard/
Dmir_promote_uniforms.c292 unsigned qword = ins->constants.u32[0] / 16; in midgard_promote_uniforms() local
305 if (!BITSET_TEST(analysis.blocks[ubo].pushed, qword)) { in midgard_promote_uniforms()
311 unsigned base = pan_lookup_pushed_ubo(&ctx->info->push, ubo, qword * 16); in midgard_promote_uniforms()
/third_party/skia/third_party/externals/swiftshader/src/System/
DTypes.hpp79 typedef ALIGN(8, uint64_t) qword; typedef
200 using qword2 = vec2<qword>;
/third_party/skia/third_party/externals/oboe/samples/RhythmGame/third_party/glm/gtx/
Draw_data.hpp42 typedef detail::uint64 qword; typedef
/third_party/skia/third_party/externals/libjpeg-turbo/simd/x86_64/
Djchuff-sse2.asm133 mov qword [buffer], tempq ; memcpy(buffer, &temp, 8);
141 ; bytes in the qword.
330 movq xmm2, qword [block + 24 * SIZEOF_WORD] ;B: w2 = 24 25 26 27 -- -- -- --
393 movq xmm1, qword [block + 44 * SIZEOF_WORD] ;G: w1 = 44 45 46 47 -- -- -- --
401 movq xmm4, qword [block + 36 * SIZEOF_WORD] ;G: w4 = 36 37 38 39 -- -- -- --
417 movlps xmm1, qword [block + 20 * SIZEOF_WORD] ;F: w1 = 20 21 22 23 37 44 51 58
/third_party/mesa3d/src/gallium/drivers/virgl/
Dvirgl_encode.h64 uint64_t qword) in virgl_encoder_write_qword() argument
66 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
Dvirgl_encode.c621 uint64_t qword; in virgl_encode_clear() local
623 STATIC_ASSERT(sizeof(qword) == sizeof(depth)); in virgl_encode_clear()
624 memcpy(&qword, &depth, sizeof(qword)); in virgl_encode_clear()
630 virgl_encoder_write_qword(ctx->cbuf, qword); in virgl_encode_clear()
/third_party/skia/third_party/externals/libjpeg-turbo/simd/nasm/
Djsimdext.inc135 %define POINTER qword ; general pointer type
191 %define MMWORD qword ; int64 (MMX register)
212 %define SIZEOF_QWORD 8 ; sizeof(qword)
219 %define QWORD_BIT 64 ; sizeof(qword)*BYTE_BIT
/third_party/libdrm/intel/tests/
Dgen6-3d.batch-ref.txt6 0x12300014: 0x00004000: qword write,
202 0x12300324: 0x00004000: qword write,
284 0x1230046c: 0x00004000: qword write,
336 0x1230053c: 0x00004000: qword write,
399 0x12300638: 0x00004000: qword write,
469 0x12300750: 0x00004000: qword write,
554 0x123008a4: 0x00004000: qword write,
606 0x12300974: 0x00004000: qword write,
669 0x12300a70: 0x00004000: qword write,
739 0x12300b88: 0x00004000: qword write,
[all …]
/third_party/skia/third_party/externals/swiftshader/src/Common/
DTypes.hpp51 typedef ALIGN(8, uint64_t) qword; typedef
/third_party/skia/third_party/externals/libjpeg-turbo/simd/i386/
Djchuff-sse2.asm178 ; bytes in the qword.
386 movq xmm2, qword [block + 24 * SIZEOF_WORD] ;B: w2 = 24 25 26 27 -- -- -- --
455 movq xmm1, qword [block + 44 * SIZEOF_WORD] ;G: w1 = 44 45 46 47 -- -- -- --
465 movq xmm4, qword [block + 36 * SIZEOF_WORD] ;G: w4 = 36 37 38 39 -- -- -- --
483 movlps xmm1, qword [block + 20 * SIZEOF_WORD] ;F: w1 = 20 21 22 23 37 44 51 58
/third_party/mesa3d/src/freedreno/decode/
Dcffdec.c404 reg_dump_gpuaddr64(const char *name, uint64_t qword, int level) in reg_dump_gpuaddr64() argument
406 dump_gpuaddr(qword, level); in reg_dump_gpuaddr64()
474 reg_disasm_gpuaddr64(const char *name, uint64_t qword, int level) in reg_disasm_gpuaddr64() argument
476 disasm_gpuaddr(name, qword, level); in reg_disasm_gpuaddr64()
545 void (*fxn64)(const char *name, uint64_t qword, int level);
878 uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; in dump_register() local
879 type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level); in dump_register()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_autotune.c630 tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_ADDR(.qword = result_iova)); in tu_autotune_begin_renderpass()
651 tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_ADDR(.qword = result_iova)); in tu_autotune_end_renderpass()
Dtu_lrz.c146 A6XX_GRAS_LRZ_BUFFER_BASE(.qword = lrz_iova), in tu6_emit_lrz_buffer()
148 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(.qword = lrz_fc_iova)); in tu6_emit_lrz_buffer()
Dtu_query.c838 A6XX_RB_SAMPLE_COUNT_ADDR(.qword = begin_iova)); in emit_begin_occlusion_query()
991 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = begin_iova)); in emit_begin_xfb_query()
1131 A6XX_RB_SAMPLE_COUNT_ADDR(.qword = end_iova)); in emit_end_occlusion_query()
1374 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = end_iova)); in emit_end_xfb_query()
Dtu_clear_blit.c262 A6XX_SP_PS_2D_SRC(.qword = va), in r2d_src_buffer()
320 A6XX_RB_2D_DST(.qword = va), in r2d_dst_buffer()
940 tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4)); in r3d_src_common()
950 tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova)); in r3d_src_common()
1119 A6XX_RB_MRT_BASE(0, .qword = va), in r3d_dst_buffer()
3164 … A6XX_SP_PS_2D_SRC(.qword = cmd->device->physical_device->gmem_base + gmem_offset), in store_cp_blit()
/third_party/mesa3d/src/intel/vulkan/
DgenX_query.c675 for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) { in emit_zero_queries() local
677 anv_address_add(slot_addr, qword * 8), in emit_zero_queries()
/third_party/mesa3d/docs/relnotes/
D20.1.8.rst64 - freedreno: Make the pack struct have a .qword for wide addresses.
/third_party/ffmpeg/libavcodec/x86/
Dvc1dsp_mc.asm98 %define shift qword r4m
/third_party/ffmpeg/libavfilter/x86/
Dvf_ssim.asm258 fld qword r0m

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