Searched refs:radv_dcc_enabled (Results 1 – 9 of 9) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_meta_fast_clear.c | 574 if (radv_dcc_enabled(image, subresourceRange->baseMipLevel) && in radv_process_color_image()
612 if (op == DCC_DECOMPRESS && !radv_dcc_enabled(image, subresourceRange->baseMipLevel + l)) in radv_process_color_image()
743 if (!radv_dcc_enabled(image, subresourceRange->baseMipLevel + l)) in radv_decompress_dcc_compute()
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| D | radv_sdma_copy_image.c | 126 bool dcc = radv_dcc_enabled(image, 0) && is_v5; in radv_sdma_v4_v5_copy_image_to_buffer()
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| D | radv_image.c | 796 if (!disable_compression && radv_dcc_enabled(image, first_level)) { in si_set_mutable_tex_desc_fields()
835 if (radv_dcc_enabled(image, first_level) && is_storage_image && enable_write_compression) in si_set_mutable_tex_desc_fields()
1046 if (radv_dcc_enabled(image, first_level)) { in gfx10_make_texture_descriptor()
2277 if (radv_dcc_enabled(image, level) && in radv_layout_can_fast_clear()
2300 if (!radv_dcc_enabled(image, level)) in radv_layout_dcc_compressed()
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| D | radv_meta_clear.c | 1396 if (!radv_dcc_enabled(image, range->baseMipLevel + l)) in radv_clear_dcc_comp_to_single()
1746 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) { in radv_can_fast_clear_color()
1816 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) { in radv_fast_clear_color()
2299 if (radv_dcc_enabled(image, ranges[i].baseMipLevel)) in radv_cmd_clear_image()
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| D | radv_meta_copy.c | 55 if (!radv_dcc_enabled(image, subres->mipLevel) && !(radv_image_is_tc_compat_htile(image))) in blit_surf_for_image_level_layer()
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| D | radv_cmd_buffer.c | 2508 assert(radv_dcc_enabled(image, range->baseMipLevel)); in radv_update_dcc_metadata()
2561 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)); in radv_set_color_clear_metadata()
2598 assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, iview->vk.base_mip_level)); in radv_update_color_clear_metadata()
2621 if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->vk.base_mip_level)) in radv_load_color_clear_metadata()
2684 radv_dcc_enabled(iview->image, iview->vk.base_mip_level) || in radv_emit_fb_mip_change_flush()
2685 radv_dcc_enabled(iview->image, cmd_buffer->state.cb_mip[i])) && in radv_emit_fb_mip_change_flush()
9409 if (radv_dcc_enabled(image, range->baseMipLevel)) { in radv_init_color_image_metadata()
9420 if (radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel)) { in radv_init_color_image_metadata()
9464 !radv_dcc_enabled(image, range->baseMipLevel)) in radv_handle_color_image_transition()
9476 if (radv_dcc_enabled(image, range->baseMipLevel)) { in radv_handle_color_image_transition()
[all …]
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| D | radv_device.c | 6192 if (!radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) in radv_init_dcc_control_reg()
6230 S_028C78_FDCC_ENABLE(radv_dcc_enabled(iview->image, iview->vk.base_mip_level)); in radv_init_dcc_control_reg()
6333 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && in radv_initialise_color_surface()
6436 if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && !iview->disable_dcc_mrt && in radv_initialise_color_surface()
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| D | radv_private.h | 2463 radv_dcc_enabled(const struct radv_image *image, unsigned level) in radv_dcc_enabled() function
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| /third_party/mesa3d/docs/relnotes/ |
| D | 21.2.0.rst | 4777 - radv: remove redundant call to radv_dcc_enabled()
4781 - radv: use radv_dcc_enabled() for the FB mip flush workaround
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