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Searched refs:rb_aligned (Results 1 – 8 of 8) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_surface_meta_address_test.c198 unsigned swizzle_mode, bool pipe_aligned, bool rb_aligned, in one_dcc_address_test() argument
215 in.dccKeyFlags.rbAligned = din.dccKeyFlags.rbAligned = rb_aligned; in one_dcc_address_test()
240 xin.flags.metaRbUnaligned = !rb_aligned; in one_dcc_address_test()
370 … for (int rb_aligned = true; rb_aligned >= (samples > 1 ? true : false); rb_aligned--) { in run_dcc_address_test() local
377 width, height, depth, bpp, samples, rb_aligned, pipe_aligned); in run_dcc_address_test()
381 rb_aligned, mrt_index, 0, 0, 0, 0)) { in run_dcc_address_test()
580 bool pipe_aligned, bool rb_aligned, unsigned mrt_index, in one_cmask_address_test() argument
599 cin.cMaskFlags.rbAligned = rb_aligned; in one_cmask_address_test()
604 cin.colorFlags.metaRbUnaligned = !rb_aligned; in one_cmask_address_test()
699 for (int rb_aligned = true; rb_aligned >= true; rb_aligned--) { in run_cmask_address_test() local
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Dac_surface_modifier_test.c71 bool rb_aligned, bool pipe_aligned) in get_addr_from_coord_base() argument
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned; in get_addr_from_coord_base()
102 dcc_input.dccKeyFlags.rbAligned = rb_aligned; in get_addr_from_coord_base()
148 surf->u.gfx9.color.dcc.rb_aligned, in generate_hash()
Dac_surface.c1592 const struct radeon_surf *surf, bool rb_aligned, in is_dcc_supported_by_DCN() argument
1603 if (info->use_display_dcc_unaligned && (rb_aligned || pipe_aligned)) in is_dcc_supported_by_DCN()
1926 surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned; in gfx9_compute_miptree()
2001 assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned); in gfx9_compute_miptree()
2380 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, in gfx9_compute_surface()
2397 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, in gfx9_compute_surface()
2408 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned, in gfx9_compute_surface()
2775 surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]); in ac_surface_set_umd_metadata()
2778 if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned) in ac_surface_set_umd_metadata()
Dac_surface.h159 uint8_t rb_aligned : 1; /* optimal for RBs */ member
/third_party/mesa3d/src/amd/vulkan/
Dradv_image.c828 .rb_aligned = 1, in si_set_mutable_tex_desc_fields()
859 .rb_aligned = 1, in si_set_mutable_tex_desc_fields()
868 S_008F24_META_RB_ALIGNED(meta.rb_aligned); in si_set_mutable_tex_desc_fields()
Dradv_device.c6276 .rb_aligned = 1, in radv_initialise_color_surface()
6285 S_028C74_RB_ALIGNED(meta.rb_aligned) | in radv_initialise_color_surface()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_descriptors.c354 .rb_aligned = 1, in si_set_mutable_tex_desc_fields()
404 .rb_aligned = 1, in si_set_mutable_tex_desc_fields()
413 S_008F24_META_RB_ALIGNED(meta.rb_aligned); in si_set_mutable_tex_desc_fields()
Dsi_state.c3357 .rb_aligned = 1, in si_emit_framebuffer_state()
3373 S_028C74_RB_ALIGNED(meta.rb_aligned) | in si_emit_framebuffer_state()