| /third_party/elfutils/tests/ |
| D | run-readelf-loc.sh | 71 [ 0] reg5
75 [ 0] reg5
112 [ 0] reg5
116 [ 0] reg5
151 [ 0] reg5
153 [ 0] reg5
188 [ 0] reg5
193 [ 0] reg5
208 [ 0] reg5
215 [ 0] reg5
[all …]
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| D | run-varlocs.sh | 57 [400500,400504) {reg5}
63 [400510,40051c) {reg5}
65 [40052b,400531) {GNU_entry_value(1) {reg5}, stack_value}
78 [400400,400406) {reg5}
80 [40040a,40040b) {GNU_entry_value(1) {reg5}, stack_value}
92 [400510,400523) {reg5}
106 [400400,400408) {reg5}
108 [400421,400423) {GNU_entry_value(1) {reg5}, stack_value}
120 [400500,400503) {reg5}
122 [400500,400503) {GNU_implicit_pointer([4a],0) {reg5}}
[all …]
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| D | run-dwarfcfi.sh | 43 reg5: same_value
60 reg5: undefined
77 reg5: undefined
94 reg5: undefined
111 reg5: same_value
128 reg5: undefined
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| D | run-readelf-zdebug-rel.sh | 100 [ 0] reg5
133 [ 0] reg5
139 [ 0] reg5
|
| D | run-readelf-zdebug.sh | 52 [ 0] reg5
58 [ 0] reg5
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| D | run-readelf-dw-form-indirect.sh | 554 [ 0] reg5
644 [ 0] reg5
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| D | run-addrcfi.sh | 38 integer reg5 (%ebp): same_value
85 integer reg5 (%ebp): same_value
137 integer reg5 (%rdi): undefined
203 integer reg5 (%rdi): undefined
307 integer reg5 (r5): undefined
1329 integer reg5 (r5): undefined
2357 integer reg5 (r5): undefined
3383 integer reg5 (%r5): undefined
3460 integer reg5 (%r5): undefined
3538 integer reg5 (r5): same_value
[all …]
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| /third_party/ffmpeg/libavcodec/loongarch/ |
| D | vp9_idct_lsx.c | 377 __m128i reg1, reg3, reg5, reg7, reg9, reg11, reg13, reg15; in vp9_idct16_1d_columns_addblk_lsx() local
385 reg4, reg5, reg6, reg7); in vp9_idct16_1d_columns_addblk_lsx()
434 VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11); in vp9_idct16_1d_columns_addblk_lsx()
436 LSX_BUTTERFLY_4_H(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vp9_idct16_1d_columns_addblk_lsx()
452 VP9_DOTP_CONST_PAIR(__lsx_vneg_h(reg5), __lsx_vneg_h(reg11), cospi_8_64, in vp9_idct16_1d_columns_addblk_lsx()
453 cospi_24_64, reg5, reg11); in vp9_idct16_1d_columns_addblk_lsx()
455 loc0 = __lsx_vadd_h(reg9, reg5); in vp9_idct16_1d_columns_addblk_lsx()
456 reg5 = __lsx_vsub_h(reg9, reg5); in vp9_idct16_1d_columns_addblk_lsx()
466 VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11); in vp9_idct16_1d_columns_addblk_lsx()
467 LSX_BUTTERFLY_4_H(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_lsx()
[all …]
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| D | vp9_mc_lsx.c | 517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
542 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, reg4, reg5); in common_vt_8t_8w_lsx()
555 out1 = FILT_8TAP_DPADD_S_H(reg3, reg4, reg5, tmp1, filter0, filter1, in common_vt_8t_8w_lsx()
559 out3 = FILT_8TAP_DPADD_S_H(reg4, reg5, tmp1, tmp3, filter0, filter1, in common_vt_8t_8w_lsx()
575 reg3 = reg5; in common_vt_8t_8w_lsx()
577 reg5 = tmp3; in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_16w_lsx() local
612 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, reg4, reg5); in common_vt_8t_16w_lsx()
630 tmp1 = FILT_8TAP_DPADD_S_H(reg3, reg4, reg5, src1, filter0, filter1, in common_vt_8t_16w_lsx()
644 tmp1 = FILT_8TAP_DPADD_S_H(reg4, reg5, src1, src3, filter0, filter1, in common_vt_8t_16w_lsx()
[all …]
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| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 968 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
1007 VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11); in vp9_idct16_1d_columns_addblk_msa()
1009 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vp9_idct16_1d_columns_addblk_msa()
1025 VP9_DOTP_CONST_PAIR((-reg5), (-reg11), cospi_8_64, cospi_24_64, reg5, in vp9_idct16_1d_columns_addblk_msa()
1028 loc0 = reg9 + reg5; in vp9_idct16_1d_columns_addblk_msa()
1029 reg5 = reg9 - reg5; in vp9_idct16_1d_columns_addblk_msa()
1039 VP9_DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11); in vp9_idct16_1d_columns_addblk_msa()
1040 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_msa()
1046 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vp9_idct16_1d_columns_addblk_msa()
[all …]
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| /third_party/node/deps/v8/src/interpreter/ |
| D | bytecode-register.cc | 106 Register reg4, Register reg5) { in AreContiguous() argument
116 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
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| D | bytecode-register.h | 88 Register reg5 = invalid_value());
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| /third_party/vixl/src/aarch64/ |
| D | registers-aarch64.h | 974 const CPURegister& reg5 = NoReg,
986 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1030 const CPURegister& reg5 = NoCPUReg,
1039 match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
1054 const CPURegister& reg5 = NoReg,
1063 even &= !reg5.IsValid() || ((reg5.GetCode() % 2) == 0);
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | vp9mc_16bpp_neon.S | 355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
360 sqrshrun \reg3\().4h, \reg5\().4s, #7
365 ld1 {\reg5\().8h}, [x7], x1
375 urhadd \reg1\().8h, \reg1\().8h, \reg5\().8h
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | register-arm64.h | 516 const CPURegister& reg5 = NoReg, const CPURegister& reg6 = NoReg,
526 const CPURegister& reg5 = NoCPUReg, const CPURegister& reg6 = NoCPUReg,
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| D | assembler-arm64.cc | 226 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
262 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
269 match &= !reg5.is_valid() || reg5.IsSameSizeAndType(reg1); in AreSameSizeAndType()
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| /third_party/node/deps/v8/src/codegen/arm/ |
| D | macro-assembler-arm.h | 37 Register reg5 = no_reg,
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| D | macro-assembler-arm.cc | 2616 Register reg4, Register reg5, in CallRecordWriteStub() argument
2618 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
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| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | macro-assembler-loong64.h | 49 Register reg5 = no_reg,
|
| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | macro-assembler-mips64.h | 64 Register reg5 = no_reg,
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| D | macro-assembler-mips.h | 54 Register reg5 = no_reg,
|
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | macro-assembler-riscv64.h | 63 Register reg5 = no_reg,
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/ |
| D | Dwarf.def | 560 HANDLE_DW_OP(0x55, reg5, 2, DWARF)
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| /third_party/node/deps/v8/src/codegen/ppc/ |
| D | macro-assembler-ppc.h | 36 Register reg5 = no_reg,
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| D | macro-assembler-ppc.cc | 3386 Register reg4, Register reg5, in CallRecordWriteStub() argument
3388 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|