| /third_party/ffmpeg/libavcodec/loongarch/ |
| D | vp9_idct_lsx.c | 376 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_lsx() local
385 reg4, reg5, reg6, reg7); in vp9_idct16_1d_columns_addblk_lsx()
409 VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6); in vp9_idct16_1d_columns_addblk_lsx()
410 LSX_BUTTERFLY_4_H(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vp9_idct16_1d_columns_addblk_lsx()
414 LSX_BUTTERFLY_4_H(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_lsx()
420 reg4 = __lsx_vsub_h(reg6, loc3); in vp9_idct16_1d_columns_addblk_lsx()
421 reg6 = __lsx_vadd_h(reg6, loc3); in vp9_idct16_1d_columns_addblk_lsx()
457 reg2 = __lsx_vadd_h(reg6, loc0); in vp9_idct16_1d_columns_addblk_lsx()
458 reg1 = __lsx_vsub_h(reg6, loc0); in vp9_idct16_1d_columns_addblk_lsx()
473 LSX_BUTTERFLY_4_H(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vp9_idct16_1d_columns_addblk_lsx()
[all …]
|
| D | vp9_mc_lsx.c | 590 __m128i reg6, reg7, reg8, reg9, reg10, reg11; in common_vt_8t_16w_lsx() local
614 reg6, reg7, reg8, reg9); in common_vt_8t_16w_lsx()
632 tmp2 = FILT_8TAP_DPADD_S_H(reg6, reg7, reg8, src4, filter0, filter1, in common_vt_8t_16w_lsx()
663 reg6 = reg8; in common_vt_8t_16w_lsx()
684 __m128i reg6, reg7, reg8, reg9, reg10, reg11; in common_vt_8t_16w_mult_lsx() local
720 reg6, reg7, reg8, reg9); in common_vt_8t_16w_mult_lsx()
739 tmp2 = FILT_8TAP_DPADD_S_H(reg6, reg7, reg8, src4, filter0, in common_vt_8t_16w_mult_lsx()
769 reg6 = reg8; in common_vt_8t_16w_mult_lsx()
1706 __m128i reg6, reg7, reg8, reg9, reg10, reg11; in common_vt_8t_and_aver_dst_16w_mult_lsx() local
1740 reg6, reg7, reg8, reg9); in common_vt_8t_and_aver_dst_16w_mult_lsx()
[all …]
|
| /third_party/elfutils/tests/ |
| D | run-dwarfcfi.sh | 44 reg6: same_value
61 reg6: same_value
78 reg6: undefined
95 reg6: undefined
112 reg6: same_value
129 reg6: undefined
|
| D | run-varlocs.sh | 64 [40051c,40052b) {reg6}
587 [40106e,401090) {reg6}
|
| D | run-addrcfi.sh | 39 integer reg6 (%esi): same_value
86 integer reg6 (%esi): same_value
138 integer reg6 (%rbp): same_value
204 integer reg6 (%rbp): same_value
308 integer reg6 (r6): undefined
1330 integer reg6 (r6): undefined
2358 integer reg6 (r6): undefined
3384 integer reg6 (%r6): same_value
3461 integer reg6 (%r6): same_value
3539 integer reg6 (r6): same_value
[all …]
|
| D | run-readelf-loc.sh | 1153 [ 0] reg6
|
| /third_party/ffmpeg/libavcodec/mips/ |
| D | vp9_idct_msa.c | 967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
982 VP9_DOTP_CONST_PAIR(reg10, reg6, cospi_12_64, cospi_20_64, reg10, reg6); in vp9_idct16_1d_columns_addblk_msa()
983 BUTTERFLY_4(reg2, reg14, reg6, reg10, loc0, loc1, reg14, reg2); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
993 reg4 = reg6 - loc3; in vp9_idct16_1d_columns_addblk_msa()
994 reg6 = reg6 + loc3; in vp9_idct16_1d_columns_addblk_msa()
1030 reg2 = reg6 + loc0; in vp9_idct16_1d_columns_addblk_msa()
1031 reg1 = reg6 - loc0; in vp9_idct16_1d_columns_addblk_msa()
1046 BUTTERFLY_4(reg12, reg14, reg13, reg3, reg8, reg6, reg7, reg5); in vp9_idct16_1d_columns_addblk_msa()
[all …]
|
| /third_party/vixl/src/aarch64/ |
| D | registers-aarch64.h | 975 const CPURegister& reg6 = NoReg,
986 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1031 const CPURegister& reg6 = NoCPUReg,
1040 match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
1055 const CPURegister& reg6 = NoReg,
1064 even &= !reg6.IsValid() || ((reg6.GetCode() % 2) == 0);
|
| /third_party/ffmpeg/libavcodec/aarch64/ |
| D | vp9mc_16bpp_neon.S | 355 .macro do_store8 reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, minreg, type
361 sqrshrun2 \reg3\().8h, \reg6\().4s, #7
366 ld1 {\reg6\().8h}, [x7], x1
376 urhadd \reg2\().8h, \reg2\().8h, \reg6\().8h
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | register-arm64.h | 516 const CPURegister& reg5 = NoReg, const CPURegister& reg6 = NoReg,
526 const CPURegister& reg5 = NoCPUReg, const CPURegister& reg6 = NoCPUReg,
|
| D | assembler-arm64.cc | 226 const CPURegister& reg5, const CPURegister& reg6, in AreAliased() argument
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
262 const CPURegister& reg5, const CPURegister& reg6, in AreSameSizeAndType() argument
270 match &= !reg6.is_valid() || reg6.IsSameSizeAndType(reg1); in AreSameSizeAndType()
|
| /third_party/node/deps/v8/src/codegen/arm/ |
| D | macro-assembler-arm.h | 38 Register reg6 = no_reg);
|
| D | macro-assembler-arm.cc | 2617 Register reg6) { in CallRecordWriteStub() argument
2618 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|
| /third_party/node/deps/v8/src/codegen/loong64/ |
| D | macro-assembler-loong64.h | 50 Register reg6 = no_reg);
|
| D | macro-assembler-loong64.cc | 4063 Register reg6) { in CallRecordWriteStub() argument
4064 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|
| /third_party/node/deps/v8/src/codegen/mips64/ |
| D | macro-assembler-mips64.h | 65 Register reg6 = no_reg);
|
| D | macro-assembler-mips64.cc | 6075 Register reg6) { in CallRecordWriteStub() argument
6076 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|
| /third_party/node/deps/v8/src/codegen/mips/ |
| D | macro-assembler-mips.h | 55 Register reg6 = no_reg);
|
| D | macro-assembler-mips.cc | 5532 Register reg6) { in CallRecordWriteStub() argument
5533 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|
| /third_party/node/deps/v8/src/codegen/riscv64/ |
| D | macro-assembler-riscv64.h | 64 Register reg6 = no_reg);
|
| D | macro-assembler-riscv64.cc | 4954 Register reg6) { in GetRegisterThatIsNotOneOf() argument
4955 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in GetRegisterThatIsNotOneOf()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/BinaryFormat/ |
| D | Dwarf.def | 561 HANDLE_DW_OP(0x56, reg6, 2, DWARF)
|
| /third_party/node/deps/v8/src/codegen/ppc/ |
| D | macro-assembler-ppc.h | 37 Register reg6 = no_reg);
|
| D | macro-assembler-ppc.cc | 3387 Register reg6) { in CallRecordWriteStub() argument
3388 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
|
| /third_party/node/deps/v8/src/codegen/s390/ |
| D | macro-assembler-s390.h | 41 Register reg6 = no_reg);
|