| /third_party/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 141 reg_(NoReg), in Operand()
148 reg_(NoReg), in Operand()
154 : reg_(reg), in Operand()
166 : reg_(reg), in Operand()
179 bool Operand::IsImmediate() const { return reg_.Is(NoReg); } in IsImmediate()
183 return reg_.IsValid() && in IsPlainRegister()
200 return reg_.IsValid() && (shift_ != NO_SHIFT); in IsShiftedRegister()
205 return reg_.IsValid() && (extend_ != NO_EXTEND); in IsExtendedRegister()
221 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
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| D | operands-aarch64.h | 353 return reg_; in GetRegister()
380 Register reg_; variable
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| /third_party/vixl/src/aarch32/ |
| D | instructions-aarch32.h | 774 uint32_t reg_; variable
777 explicit SpecialRegister(uint32_t reg) : reg_(reg) {} in SpecialRegister()
779 : reg_(reg) {} in SpecialRegister()
780 uint32_t GetReg() const { return reg_; } in GetReg()
782 bool Is(SpecialRegister value) const { return reg_ == value.reg_; } in Is()
783 bool Is(uint32_t value) const { return reg_ == value; } in Is()
784 bool IsNot(uint32_t value) const { return reg_ != value; } in IsNot()
828 uint32_t reg_; variable
831 explicit BankedRegister(unsigned reg) : reg_(reg) {} in BankedRegister()
833 : reg_(reg) {} in BankedRegister()
[all …]
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| D | instructions-aarch32.cc | 209 switch (reg_) { in GetName()
221 switch (reg_) { in GetName()
289 switch (reg_) { in GetName()
362 switch (reg_) { in GetName()
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| D | disasm-aarch32.h | 166 DRegister reg_; variable
171 : reg_(reg), index_(index) {} in IndexedRegisterPrinter()
172 DRegister GetReg() const { return reg_; } in GetReg()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64-inl.h | 239 Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
243 : immediate_(t, rmode), reg_(NoReg) {}
247 reg_(reg),
258 reg_(reg),
271 DCHECK_IMPLIES(heap_object_request_.has_value(), reg_ == NoReg);
284 return reg_ == NoReg && !IsHeapObjectRequest();
288 return reg_.is_valid() && (shift_ != NO_SHIFT);
292 return reg_.is_valid() && (extend_ != NO_EXTEND);
306 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
311 DCHECK(reg_.Is64Bits());
[all …]
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| D | assembler-arm64.h | 125 Register reg_; variable
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| /third_party/mesa3d/src/amd/compiler/ |
| D | aco_ir.h | 491 : reg_(PhysReg{128}), isTemp_(false), isFixed_(true), isConstant_(false), isKill_(false), in Operand()
764 constexpr PhysReg physReg() const noexcept { return reg_; } in physReg()
769 reg_ = reg; in setFixed()
774 constexpr bool isLiteral() const noexcept { return isConstant() && reg_ == 255; } in isLiteral()
788 if (reg_ <= 192) in constantValue64()
789 return reg_ - 128; in constantValue64()
790 else if (reg_ <= 208) in constantValue64()
791 return 0xFFFFFFFFFFFFFFFF - (reg_ - 193); in constantValue64()
793 switch (reg_) { in constantValue64()
894 PhysReg reg_; variable
[all …]
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| D | aco_register_allocation.cpp | 60 assignment(PhysReg reg_, RegClass rc_) : reg(reg_), rc(rc_), assigned(-1) {} in assignment()
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| /third_party/node/deps/v8/src/regexp/ |
| D | regexp-compiler.h | 238 : action_type_(action_type), reg_(reg), next_(nullptr) {} in DeferredAction()
241 int reg() { return reg_; } in reg()
246 int reg_; variable
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| D | regexp-nodes.h | 576 Guard(int reg, Relation op, int value) : reg_(reg), op_(op), value_(value) {} in Guard()
577 int reg() { return reg_; } in reg()
582 int reg_;
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| /third_party/ffmpeg/libavcodec/x86/ |
| D | vp9lpf_16bpp.asm | 49 %define reg_%4 m%2
54 %define reg_%4 [%3]
66 %undef reg_%4
74 %define reg_%3 m%1
77 %define reg_%3 [%2]
148 pand %1, reg_%3 ; apply mask
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| D | vp9itxfm_16bpp.asm | 458 %define reg_%4 m%2
463 %define reg_%4 [%3]
475 %undef reg_%4
483 %define reg_%3 m%1
486 %define reg_%3 [%2]
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| D | vp9intrapred_16bpp.asm | 53 %define reg_%4 m%2
58 %define reg_%4 [%3]
70 %undef reg_%4
78 %define reg_%3 m%1
81 %define reg_%3 [%2]
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| /third_party/skia/tools/fiddle/ |
| D | examples.h | 45 sk_tools::Registry<fiddle::Example> reg_##NAME( \
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| /third_party/node/deps/v8/src/wasm/baseline/ |
| D | liftoff-assembler.h | 118 : loc_(kRegister), kind_(kind), reg_(r), spill_offset_(offset) { in VarState()
130 bool is_gp_reg() const { return loc_ == kRegister && reg_.is_gp(); } in is_gp_reg()
131 bool is_fp_reg() const { return loc_ == kRegister && reg_.is_fp(); } in is_fp_reg()
157 return reg_; in reg()
165 reg_ = r; in MakeRegister()
180 reg_ = src.reg(); in Copy()
193 LiftoffRegister reg_; // used if loc_ == kRegister member
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| /third_party/node/deps/v8/src/compiler/backend/ |
| D | register-allocator.h | 738 int reg() { return reg_; } in reg()
741 DCHECK_EQ(reg_, kUnassignedRegister); in set_reg()
742 reg_ = reg; in set_reg()
798 int reg_ = kUnassignedRegister; variable
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| /third_party/elfutils/libdw/ |
| D | cfi.c | 124 fs->regs[regno].rule = reg_##r_rule; \ in execute_cfi()
|