| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 289 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
444 TRI->regsOverlap(DependenceMO.getReg(), PointerReg)) && in canHoistInst()
603 TRI->regsOverlap(MO.getReg(), PointerReg); in analyzeBlockForNullChecks()
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| D | MachineCopyPropagation.cpp | 456 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg())) in hasImplicitOverlap()
562 if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(), in ForwardCopyPropagateBlock()
813 !TRI->regsOverlap(MI->getOperand(0).getReg(), in BackwardCopyPropagateBlock()
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| D | ProcessImplicitDefs.cpp | 106 !TRI->regsOverlap(Reg, UserReg)) in processImplicitDef()
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| D | CriticalAntiDepBreaker.cpp | 434 if (TRI->regsOverlap(NewReg, *it)) { in findSuitableFreeRegister()
628 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | MachineInstrBundle.cpp | 333 if (!TRI->regsOverlap(MOReg, Reg)) in AnalyzePhysRegInBundle()
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| D | MachineInstr.cpp | 952 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) in findRegisterUseOperandIdx()
1007 Found = TRI->regsOverlap(MOReg, Reg); in findRegisterDefOperandIdx()
1859 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
1965 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); })) in setPhysRegsDeadExcept()
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| D | RegAllocPBQP.cpp | 419 if (TRI.regsOverlap(PRegN, PRegM)) { in createInterferenceEdge()
572 if (TRI.regsOverlap(reg, CSR[i])) in isACalleeSavedRegister()
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| D | VirtRegMap.cpp | 425 if (TRI->regsOverlap(Dst->getOperand(0).getReg(), in expandCopyBundle()
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| D | MachineBasicBlock.cpp | 1413 if (TRI->regsOverlap(LI.PhysReg, Reg)) in computeRegisterLiveness()
1472 if (TRI->regsOverlap(LI.PhysReg, Reg)) in computeRegisterLiveness()
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| D | TwoAddressInstructionPass.cpp | 566 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
573 if (TRI->regsOverlap(R, Reg)) in regOverlapsSet()
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| D | MachineCSE.cpp | 240 if (!TRI->regsOverlap(MO.getReg(), Reg)) in isPhysDefTriviallyDead()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 167 if (TRI->regsOverlap(Reg, X86::XMM4) || in CC_X86_64_VectorCall()
168 TRI->regsOverlap(Reg, X86::XMM5)) in CC_X86_64_VectorCall()
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| D | X86CallFrameOptimization.cpp | 341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
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| D | X86FixupBWInsts.cpp | 274 TRI->regsOverlap(SuperDestReg, MO.getReg())) in getSuperRegDestIfDead()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 759 TRI->regsOverlap(MOP.getReg(), DefReg); in forAllMIsUntilDef()
827 TRI->regsOverlap(MOP.getReg(), RegToRename)) { in mergePairedInsns()
838 TRI->regsOverlap(MOP.getReg(), RegToRename)) { in mergePairedInsns()
861 !TRI->regsOverlap(MOP.getReg(), *RenameReg); in mergePairedInsns()
1298 TRI->regsOverlap(RegToRename, MOP.getReg()); in canRenameUpToDef()
1347 !TRI->regsOverlap(MOP.getReg(), RegToRename)) in canRenameUpToDef()
1360 !TRI->regsOverlap(MOP.getReg(), RegToRename)) in canRenameUpToDef()
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| D | AArch64PBQPRegAlloc.cpp | 196 if (livesOverlap && TRI->regsOverlap(pRd, pRa)) in addIntraChainConstraint()
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| D | AArch64CallLowering.cpp | 883 return TRI->regsOverlap(Use.getReg(), ForwardedReg); in lowerTailCall()
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| D | AArch64AsmPrinter.cpp | 626 assert(RI->regsOverlap(RegToPrint, Reg)); in printAsmRegInClass()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 733 TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg); in checkVALUHazardsHelper()
1267 return TRI.regsOverlap(DstReg, Reg); in checkMAIHazards()
1309 return TRI.regsOverlap(Reg, DstReg); in checkMAIHazards()
1344 return TRI.regsOverlap(Reg, DstReg); in checkMAIHazards()
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| D | SIShrinkInstructions.cpp | 398 if (TRI.regsOverlap(Reg, MO.getReg())) in instAccessReg()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1735 if (isLd && TRI->regsOverlap(EvenReg, BaseReg)) { in FixInvalidRegPairOp()
1736 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1820 if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) { in LoadStoreMultipleOpti()
2132 if (MO.isDef() && TRI->regsOverlap(Reg, Base)) in IsSafeAndProfitableToMove()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 380 bool regsOverlap(Register regA, Register regB) const { in regsOverlap() function
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 151 if (TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 2863 if (TRI->regsOverlap(*ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
2902 if (TRI->regsOverlap(Reg, SUReg)) in canClobberPhysRegDefs()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfDebug.cpp | 598 if (TRI->regsOverlap(FwdReg, MO.getReg())) { in collectCallSiteParameters()
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