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Searched refs:rsrc2 (Results 1 – 9 of 9) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_binary.c67 conf->rsrc2 = value; in ac_parse_shader_binary_config()
71 conf->rsrc2 = value; in ac_parse_shader_binary_config()
75 conf->rsrc2 = value; in ac_parse_shader_binary_config()
79 conf->rsrc2 = value; in ac_parse_shader_binary_config()
83 conf->rsrc2 = value; in ac_parse_shader_binary_config()
Dac_binary.h49 unsigned rsrc2; member
Dac_rtld.c557 assert(config->rsrc1 == 0 && config->rsrc2 == 0); in ac_rtld_read_config()
559 config->rsrc2 = c.rsrc2; in ac_rtld_read_config()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32; in code_object_to_config() local
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2)); in code_object_to_config()
104 out_config->rsrc2 = rsrc2; in code_object_to_config()
210 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | in si_create_compute_state_async()
538 config->rsrc2 &= C_00B84C_LDS_SIZE; in si_switch_compute_shader()
539 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks); in si_switch_compute_shader()
582 radeon_emit(config->rsrc2); in si_switch_compute_shader()
587 config->rsrc1, config->rsrc2); in si_switch_compute_shader()
Dsi_state_shaders.cpp701 shader->config.rsrc2 = in si_shader_ls()
733 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) | in si_shader_hs()
737 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); in si_shader_hs()
739 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); in si_shader_hs()
745 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) | in si_shader_hs()
762 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2); in si_shader_hs()
1111 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) | in si_shader_gs() local
1118 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5); in si_shader_gs()
1121 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5); in si_shader_gs()
1125 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2); in si_shader_gs()
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Dsi_state_draw.cpp807 unsigned hs_rsrc2 = ls_current->config.rsrc2; in si_emit_derived_tess_state()
823 unsigned ls_rsrc2 = ls_current->config.rsrc2; in si_emit_derived_tess_state()
/third_party/mesa3d/src/amd/vulkan/
Dradv_shader.c1674 config_out->rsrc2 = S_00B12C_USER_SGPR(args->num_user_sgprs) | in radv_postprocess_config()
1685 config_out->rsrc2 |= in radv_postprocess_config()
1695 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(args->num_user_sgprs >> 5); in radv_postprocess_config()
1698 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(args->num_user_sgprs >> 5); in radv_postprocess_config()
1707 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) | S_00B22C_EXCP_EN(excp_en); in radv_postprocess_config()
1712 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en); in radv_postprocess_config()
1718 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en); in radv_postprocess_config()
1720 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks); in radv_postprocess_config()
1734 config_out->rsrc2 |= in radv_postprocess_config()
1738 config_out->rsrc2 |= in radv_postprocess_config()
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Dradv_pipeline.c5657 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_emit_hw_vs()
5735 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_emit_hw_es()
5745 uint32_t rsrc2 = shader->config.rsrc2; in radv_pipeline_emit_hw_ls() local
5749 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks); in radv_pipeline_emit_hw_ls()
5751 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); in radv_pipeline_emit_hw_ls()
5755 radeon_emit(cs, rsrc2); in radv_pipeline_emit_hw_ls()
5775 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_emit_hw_ngg()
5953 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_emit_hw_hs()
5959 radeon_emit(cs, shader->config.rsrc2); in radv_pipeline_emit_hw_hs()
6148 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size)); in radv_pipeline_emit_hw_gs()
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Dradv_cmd_buffer.c1582 (v->config.rsrc2 & C_00B22C_LDS_SIZE) | in radv_emit_graphics_pipeline()
7569 uint32_t rsrc2 = v->config.rsrc2; in radv_emit_ngg_culling_state() local
7574 … rsrc2 = (rsrc2 & C_00B22C_LDS_SIZE) | S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling); in radv_emit_ngg_culling_state()
7582 radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2); in radv_emit_ngg_culling_state()