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Searched refs:si_resource (Results 1 – 25 of 27) sorted by relevance

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/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_buffer.c39 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource, in si_buffer_map()
45 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size, in si_init_resource_fields()
168 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res) in si_alloc_resource()
218 struct si_resource *buffer = si_resource(buf); in si_resource_destroy()
232 struct si_resource *resource = &tex->buffer; in si_resource_destroy()
250 static bool si_invalidate_buffer(struct si_context *sctx, struct si_resource *buf) in si_invalidate_buffer()
285 struct si_resource *sdst = si_resource(dst); in si_replace_buffer_storage()
286 struct si_resource *ssrc = si_resource(src); in si_replace_buffer_storage()
306 struct si_resource *buf = si_resource(resource); in si_invalidate_resource()
316 struct si_resource *staging, unsigned offset) in si_buffer_get_transfer()
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Dsi_pipe.h324 struct si_resource { struct
372 struct si_resource *staging; argument
376 struct si_resource buffer;
390 struct si_resource *cmask_buffer;
705 struct si_resource *attribute_ring;
809 struct si_resource *buf_filled_size;
904 struct si_resource *trace_buf;
948 struct si_resource *eop_bug_scratch;
949 struct si_resource *eop_bug_scratch_tmz;
959 struct si_resource *shadowed_regs;
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Dsi_cp_dma.c161 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(dst), in si_cp_dma_prepare()
164 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(src), in si_cp_dma_prepare()
194 struct si_resource *sdst = si_resource(dst); in si_cp_dma_clear_buffer()
304 util_range_add(dst, &si_resource(dst)->valid_buffer_range, dst_offset, dst_offset + size); in si_cp_dma_copy_buffer()
307 dst_offset += si_resource(dst)->gpu_address; in si_cp_dma_copy_buffer()
310 src_offset += si_resource(src)->gpu_address; in si_cp_dma_copy_buffer()
337 bool secure = src && (si_resource(src)->flags & RADEON_FLAG_ENCRYPTED); in si_cp_dma_copy_buffer()
338 assert(!secure || (!dst || (si_resource(dst)->flags & RADEON_FLAG_ENCRYPTED))); in si_cp_dma_copy_buffer()
393 si_resource(dst)->TC_L2_dirty = true; in si_cp_dma_copy_buffer()
447 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset, in si_cp_write_data()
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Dsi_query.h41 struct si_resource;
173 void (*emit_start)(struct si_context *, struct si_query_hw *, struct si_resource *buffer,
175 void (*emit_stop)(struct si_context *, struct si_query_hw *, struct si_resource *buffer,
184 struct si_resource *buf;
218 struct si_resource *workaround_buf;
244 struct si_resource *buf;
Dsi_descriptors.c191 static inline unsigned si_get_sampler_view_priority(struct si_resource *res) in si_get_sampler_view_priority()
260 struct si_resource *res = si_resource(sview->base.texture); in si_sampler_views_check_encrypted()
268 static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, uint32_t *state) in si_set_buf_desc_address()
738 struct si_resource *res = si_resource(view->resource); in si_mark_image_range_valid()
751 struct si_resource *res; in si_set_shader_image_desc()
753 res = si_resource(view->resource); in si_set_shader_image_desc()
835 struct si_resource *res; in si_set_shader_image()
842 res = si_resource(view->resource); in si_set_shader_image()
1121 sctx, &sctx->gfx_cs, si_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
1135 if (si_resource(buffers->buffers[i])->flags & RADEON_FLAG_ENCRYPTED) in si_buffer_resources_check_encrypted()
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Dsi_compute.c366 va = si_resource(resources[i])->gpu_address; in si_set_global_binding()
666 struct si_resource *dispatch_buf = NULL; in si_setup_user_sgprs_co_v2()
727 struct si_resource *input_buffer = NULL; in si_upload_compute_input()
776 COPY_DATA_SRC_MEM, si_resource(info->indirect), in si_setup_nir_user_data()
859 uint64_t base_va = si_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
861 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(info->indirect), in si_emit_dispatch_packets()
909 struct si_resource *res = si_resource(sview->base.texture); in si_check_needs_implicit_sync()
922 struct si_resource *res = si_resource(sview->resource); in si_check_needs_implicit_sync()
970 if (sctx->gfx_level <= GFX8 && si_resource(info->indirect)->TC_L2_dirty) { in si_launch_grid()
972 si_resource(info->indirect)->TC_L2_dirty = false; in si_launch_grid()
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Dradeon_video.c65 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED, usage, size)); in si_vid_create_buffer()
76 buffer->res = si_resource(pipe_buffer_create(screen, PIPE_BIND_SHARED | PIPE_BIND_PROTECTED, in si_vid_create_tmz_buffer()
Dsi_state_streamout.c43 struct si_resource *buf = si_resource(buffer); in si_create_so_target()
99 si_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true; in si_set_streamout_targets()
203 si_resource(targets[i]->buffer)->bind_history |= SI_BIND_STREAMOUT_BUFFER; in si_set_streamout_targets()
Dsi_state_draw.cpp412 uint64_t address = si_resource(buf)->gpu_address + offset; in si_cp_dma_prefetch_inline()
774 si_resource(sctx->tess_rings_tmz) : si_resource(sctx->tess_rings))->gpu_address; in si_emit_derived_tess_state()
1531 index_va = si_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
1533 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indexbuf), in si_emit_draw_packets()
1554 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
1565 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(indirect->buffer), in si_emit_draw_packets()
1592 struct si_resource *params_buf = si_resource(indirect->indirect_draw_count); in si_emit_draw_packets()
1810 struct si_resource *buf = si_resource(vb->buffer.resource); in si_set_vb_descriptor()
1970 si_resource(vstate->b.input.vbuffer.buffer.resource), in si_upload_and_prefetch_VB_descriptors()
1992 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(vb->buffer.resource), in si_upload_and_prefetch_VB_descriptors()
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Dsi_compute_blit.c106 static bool si_is_buffer_idle(struct si_context *sctx, struct si_resource *buf, in si_is_buffer_idle()
119 if (si_is_buffer_idle(sctx, si_resource(dst), RADEON_USAGE_READWRITE) && in si_improve_sync_flags()
120 (!src || si_is_buffer_idle(sctx, si_resource(src), RADEON_USAGE_WRITE))) { in si_improve_sync_flags()
137 unsigned bind_history = si_resource(dst)->bind_history | in si_improve_sync_flags()
138 (src ? si_resource(src)->bind_history : 0); in si_improve_sync_flags()
252 si_resource(buffers[u_bit_scan(&writeable_bitmask)].buffer)->TC_L2_dirty = true; in si_launch_grid_internal_ssbos()
521 if (sctx->screen->info.has_dedicated_vram && si_resource(dst)->domains & RADEON_DOMAIN_VRAM && in si_copy_buffer()
522 si_resource(src)->domains & RADEON_DOMAIN_VRAM && size > compute_min_size && in si_copy_buffer()
Dsi_fence.c35 struct si_resource *buf;
69 struct si_resource *buf, uint64_t va, uint32_t new_fence, in si_cp_release_mem()
92 struct si_resource *scratch; in si_cp_release_mem()
131 struct si_resource *scratch = ctx->eop_bug_scratch; in si_cp_release_mem()
Dradeon_video.h42 struct si_resource *res;
Dsi_gfx_cs.c193 si_resource(pipe_buffer_create(ctx->b.screen, 0, PIPE_USAGE_STAGING, 4)); in si_begin_gfx_cs_debug()
430 … unlikely(is_secure) ? si_resource(ctx->tess_rings_tmz) : si_resource(ctx->tess_rings), in si_begin_new_gfx_cs()
616 static struct si_resource *si_get_wait_mem_scratch_bo(struct si_context *ctx, in si_get_wait_mem_scratch_bo()
820 struct si_resource *wait_mem_scratch = in gfx10_emit_cache_flush()
1054 struct si_resource* wait_mem_scratch = in si_emit_cache_flush()
Dsi_state.h143 struct si_resource *instance_divisor_factor_buffer;
435 struct si_resource *buffer;
538 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
Dsi_query.c578 buffer->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in si_query_buffer_alloc()
681 struct si_resource *buffer, uint64_t va);
683 struct si_resource *buffer, uint64_t va);
807 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_start()
927 struct si_resource *buffer, uint64_t va) in si_query_hw_do_emit_stop()
1037 static void emit_set_predicate(struct si_context *ctx, struct si_resource *buf, uint64_t va, in emit_set_predicate()
1642 si_resource(resource)->TC_L2_dirty = true; in si_query_hw_get_result_resource()
Dsi_shader.h851 struct si_resource *bo;
852 struct si_resource *scratch_bo;
Dsi_cp_reg_shadowing.c32 struct si_resource *shadow_regs) in si_build_load_reg()
Dsi_texture.c663 struct si_resource *res = si_resource(resource); in si_texture_get_handle()
682 res = si_resource(resource); in si_texture_get_handle()
922 struct si_resource *resource; in si_texture_create_object()
1345 bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned level, in si_texture_commit()
1829 struct si_resource *buf; in si_texture_transfer_map()
1969 struct si_resource *buf = stransfer->staging ? stransfer->staging : &tex->buffer; in si_texture_transfer_unmap()
Dsi_perfcounter.c125 static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_start()
144 static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer, uint64_t va) in si_pc_emit_stop()
Dsi_pipe.c582 sctx->border_color_buffer = si_resource(pipe_buffer_create( in si_create_context()
842 return !ws->buffer_wait(ws, si_resource(resource)->buf, 0, in si_is_resource_busy()
1007 si_resource(buf)->gpu_address = 0; /* cause a VM fault */ in si_test_vmfault()
Dgfx10_query.c99 qbuf->buf = si_resource(pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size)); in gfx10_alloc_query_buffer()
Dsi_state.c3900 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf, in si_make_buffer_descriptor()
4555 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format, in si_create_sampler_view()
5072 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create( in si_create_vertex_elements()
5175 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER; in si_set_vertex_buffers()
5195 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER; in si_set_vertex_buffers()
Dsi_debug.c612 struct si_resource *buf;
Dsi_state_shaders.cpp4108 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->hs.tess_offchip_ring_size; in si_init_tess_factor_ring()
4123 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(sctx->tess_rings), in si_init_tess_factor_ring()
4154 uint64_t va = si_resource(tf_ring)->gpu_address + sctx->screen->hs.tess_offchip_ring_size; in si_init_tess_factor_ring()
Dradeon_vcn_dec.c1907 decode->dt_size = si_resource(((struct vl_video_buffer *)target)->resources[0])->buf->size + in rvcn_dec_message_decode()
1908 si_resource(((struct vl_video_buffer *)target)->resources[1])->buf->size; in rvcn_dec_message_decode()

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