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Searched refs:size_written (Results 1 – 25 of 32) sorted by relevance

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/third_party/mesa3d/src/intel/compiler/
Dbrw_fs_copy_propagation.cpp51 unsigned size_written; member
209 if (regions_overlap(inst->dst, inst->size_written, in setup_initial_values()
210 entry->dst, entry->size_written)) in setup_initial_values()
236 if (regions_overlap(inst->dst, inst->size_written, in setup_initial_values()
268 for (unsigned off = 0; off < acp[i]->size_written; off += REG_SIZE) { in setup_initial_values()
488 entry->dst, entry->size_written)) in try_copy_propagate()
766 entry->dst, entry->size_written)) in try_constant_propagate()
1004 !regions_overlap(inst->dst, inst->size_written, in can_propagate_from()
1044 if (regions_overlap(entry->dst, entry->size_written, in opt_copy_propagation_local()
1045 inst->dst, inst->size_written)) in opt_copy_propagation_local()
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Dbrw_fs_register_coalesce.cpp165 inst->dst, inst->size_written)) in can_coalesce_vars()
173 if (regions_overlap(scan_inst->dst, scan_inst->size_written, in can_coalesce_vars()
174 inst->dst, inst->size_written)) in can_coalesce_vars()
178 if (regions_overlap(scan_inst->dst, scan_inst->size_written, in can_coalesce_vars()
246 for (unsigned i = 0; i < MAX2(inst->size_written / REG_SIZE, 1); i++) in register_coalesce()
Dbrw_vec4.cpp201 return size_written > REG_SIZE; in has_source_and_destination_hazard()
1019 scan_inst->dst, scan_inst->size_written)) { in opt_register_coalesce()
1067 if (scan_inst->size_written != inst->size_written) in opt_register_coalesce()
1081 if (DIV_ROUND_UP(scan_inst->size_written, in opt_register_coalesce()
1111 if (regions_overlap(inst->dst, inst->size_written, in opt_register_coalesce()
1112 scan_inst->dst, scan_inst->size_written) && in opt_register_coalesce()
1130 if (regions_overlap(inst->dst, inst->size_written, in opt_register_coalesce()
1379 alloc.sizes[inst->dst.nr] * REG_SIZE != inst->size_written)) { in dump_instruction()
1701 const unsigned size_written = type_sz(inst->dst.type); in fixup_3src_null_dest() local
1702 const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE); in fixup_3src_null_dest()
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Dbrw_fs_cse.cpp191 a->size_written == b->size_written && in instructions_match()
304 assert(inst->size_written == entry->generator->size_written); in opt_cse_local()
353 if (regions_overlap(inst->dst, inst->size_written, in opt_cse_local()
Dbrw_vec4_cse.cpp159 a->size_written == b->size_written && in instructions_match()
216 DIV_ROUND_UP(entry->generator->size_written, component_size); in opt_cse_local()
237 DIV_ROUND_UP(inst->size_written, component_size); in opt_cse_local()
Dbrw_fs_lower_regioning.cpp431 assert(inst->size_written == inst->dst.component_size(inst->exec_size)); in lower_dst_modifiers()
433 inst->size_written = inst->dst.component_size(inst->exec_size); in lower_dst_modifiers()
534 assert(inst->size_written == inst->dst.component_size(inst->exec_size)); in lower_dst_region()
536 inst->size_written = inst->dst.component_size(inst->exec_size); in lower_dst_region()
572 assert(sub_inst.size_written == sub_inst.dst.component_size(sub_inst.exec_size)); in lower_exec_type()
Dbrw_fs.cpp80 this->size_written = dst.component_size(exec_size); in init()
83 this->size_written = 0; in init()
197 inst->size_written = 4 * vec4_result.component_size(inst->exec_size); in VARYING_PULL_CONSTANT_LOAD()
1055 return flag_mask(dst, size_written); in flags_written()
1651 send->size_written = num_regs * REG_SIZE; in assign_curb_setup()
2180 assert(inst->size_written == alloc.sizes[inst->dst.nr] * REG_SIZE); in split_virtual_grfs()
2254 assert(inst->size_written % REG_SIZE == 0); in split_virtual_grfs()
2256 while (reg_offset < inst->size_written / REG_SIZE) { in split_virtual_grfs()
2947 lp->size_written -= lp2->size_written; in opt_split_sends()
2949 lp->dst = fs_reg(VGRF, alloc.allocate(lp->size_written / REG_SIZE), lp->dst.type); in opt_split_sends()
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Dbrw_vec4_dead_code_eliminate.cpp60 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
142 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in dead_code_eliminate()
Dbrw_ir_fs.h449 inst->size_written - in regs_written()
450 MIN2(inst->size_written, reg_padding(inst->dst)), in regs_written()
616 if (regions_overlap(inst->dst, inst->size_written, in is_copy_payload()
687 alloc.sizes[inst->src[0].nr] * REG_SIZE == inst->size_written; in is_coalescing_payload()
Dbrw_fs_nir.cpp2170 inst->size_written = 2 * dst.component_size(inst->exec_size); in emit_pixel_interpolater_send()
2626 inst->size_written = read_components * in emit_gs_input_load()
2635 inst->size_written = num_components * in emit_gs_input_load()
2652 inst->size_written = read_components * in emit_gs_input_load()
2661 inst->size_written = num_components * in emit_gs_input_load()
2969 inst->size_written = (num_components + first_component) * in nir_emit_tcs_intrinsic()
2979 inst->size_written = 4 * REG_SIZE; in nir_emit_tcs_intrinsic()
3012 inst->size_written = read_components * REG_SIZE; in nir_emit_tcs_intrinsic()
3020 inst->size_written = instr->num_components * REG_SIZE; in nir_emit_tcs_intrinsic()
3037 inst->size_written = read_components * REG_SIZE; in nir_emit_tcs_intrinsic()
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Dbrw_fs_cmod_propagation.cpp181 if (regions_overlap(scan_inst->dst, scan_inst->size_written, in cmod_propagate_not()
288 if (regions_overlap(scan_inst->dst, scan_inst->size_written, in opt_cmod_propagation_local()
Dbrw_fs_generator.cpp330 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE; in generate_send()
445 assert(inst->size_written % REG_SIZE == 0); in generate_fb_read()
451 inst->header_size, inst->size_written / REG_SIZE, in generate_fb_read()
996 assert(inst->size_written % REG_SIZE == 0); in generate_tex()
1208 inst->size_written / REG_SIZE, in generate_tex()
1555 brw_message_desc(devinfo, 1, DIV_ROUND_UP(inst->size_written, in generate_uniform_pull_constant_load_gfx7()
1583 DIV_ROUND_UP(inst->size_written, REG_SIZE), true) | in generate_uniform_pull_constant_load_gfx7()
1624 assert(inst->size_written == 8 * REG_SIZE); in generate_varying_pull_constant_load_gfx4()
1660 assert(inst->size_written % REG_SIZE == 0); in generate_pixel_interpolator_query()
1673 inst->size_written / REG_SIZE); in generate_pixel_interpolator_query()
Dbrw_fs_builder.h772 inst->size_written = header_size * REG_SIZE; in LOAD_PAYLOAD()
774 inst->size_written += dispatch_width() * type_sz(src[i].type) * in LOAD_PAYLOAD()
787 inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE; in UNDEF()
Dbrw_ir.h162 unsigned size_written; /**< Data written to the destination register in bytes. */ member
Dbrw_vec4_copy_propagation.cpp76 return regions_overlap(*src, REG_SIZE, inst->dst, inst->size_written) && in is_channel_updated()
325 if (inst->size_written > REG_SIZE && is_uniform(value)) in try_copy_propagate()
Dbrw_fs_saturate_propagation.cpp70 regions_overlap(scan_inst->dst, scan_inst->size_written, in opt_saturate_propagation_local()
Dbrw_vec4_surface_builder.cpp130 inst->size_written = ret_sz * REG_SIZE; in emit_send()
Dbrw_schedule_instructions.cpp1668 if (inst->size_written <= 4 * inst->exec_size && in choose_instruction_to_schedule()
1669 chosen_inst->size_written > 4 * chosen_inst->exec_size) { in choose_instruction_to_schedule()
1673 } else if (inst->size_written > chosen_inst->size_written) { in choose_instruction_to_schedule()
Dbrw_vec4_live_variables.cpp103 for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) { in setup_def_use()
Dbrw_vec4_cmod_propagation.cpp146 scan_inst->dst, scan_inst->size_written)) { in opt_cmod_propagation_local()
Dbrw_lower_logical_sends.cpp40 assert(inst->size_written % REG_SIZE == 0); in lower_urb_read_logical_send()
1084 unsigned mlen = load_payload_inst->size_written / REG_SIZE; in lower_sampler_logical_send_gfx7()
2274 assert(inst->size_written == 16 * inst->exec_size); in lower_lsc_varying_pull_constant_logical_send()
2275 inst->size_written /= 4; in lower_lsc_varying_pull_constant_logical_send()
2354 assert(inst->size_written == 16 * inst->exec_size); in lower_varying_pull_constant_logical_send()
2355 inst->size_written /= 4; in lower_varying_pull_constant_logical_send()
Dbrw_ir_vec4.h421 return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + inst->size_written, in regs_written()
Dbrw_vec4_builder.h316 inst->size_written = inst->exec_size * type_sz(inst->dst.type); in emit()
Dbrw_fs_reg_allocate.cpp783 unspill_inst->size_written = reg_size * REG_SIZE; in emit_unspill()
852 spill_inst->size_written = 0; in emit_spill()
/third_party/PyYAML/yaml/
D_yaml.pxd245 char *output, size_t size, size_t *size_written)

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