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Searched refs:sltu (Results 1 – 25 of 33) sorted by relevance

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/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/bn/
Dbn-mips.S52 sltu $2,$13,$2 # All manuals say it "compares 32-bit
60 sltu $1,$13,$1
67 sltu $2,$15,$2
73 sltu $1,$15,$1
81 sltu $2,$9,$2
87 sltu $1,$9,$1
94 sltu $2,$11,$2
99 sltu $1,$11,$1
115 sltu $2,$13,$2
120 sltu $1,$13,$1
[all …]
Dmips-mont.S68 sltu $1,$24,$10
86 sltu $1,$10,$11
87 sltu $2,$24,$25
94 sltu $1,$24,$10
99 sltu $2,$22,$9
108 sltu $1,$10,$11
112 sltu $2,$24,$25
115 sltu $1,$24,$10
121 sltu $1,$25,$11
141 sltu $1,$10,$20
[all …]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/bn/
Dbn-mips.S52 sltu $2,$13,$2 # All manuals say it "compares 32-bit
60 sltu $1,$13,$1
67 sltu $2,$15,$2
73 sltu $1,$15,$1
81 sltu $2,$9,$2
87 sltu $1,$9,$1
94 sltu $2,$11,$2
99 sltu $1,$11,$1
115 sltu $2,$13,$2
120 sltu $1,$13,$1
[all …]
Dmips-mont.S68 sltu $1,$24,$10
86 sltu $1,$10,$11
87 sltu $2,$24,$25
94 sltu $1,$24,$10
99 sltu $2,$22,$9
108 sltu $1,$10,$11
112 sltu $2,$24,$25
115 sltu $1,$24,$10
121 sltu $1,$25,$11
141 sltu $1,$10,$20
[all …]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm/crypto/poly1305/
Dpoly1305-mips.S186 sltu $10,$12,$8
187 sltu $11,$13,$9
192 sltu $10,$13,$10
207 sltu $10,$8,$10
212 sltu $1,$9,$1
223 sltu $10,$9,$10
229 sltu $1,$9,$1
238 sltu $10,$12,$10
240 sltu $10,$13,$10
269 sltu $2,$9,$2
[all …]
/third_party/node/deps/openssl/config/archs/linux64-mips64/asm_avx2/crypto/poly1305/
Dpoly1305-mips.S186 sltu $10,$12,$8
187 sltu $11,$13,$9
192 sltu $10,$13,$10
207 sltu $10,$8,$10
212 sltu $1,$9,$1
223 sltu $10,$9,$10
229 sltu $1,$9,$1
238 sltu $10,$12,$10
240 sltu $10,$13,$10
269 sltu $2,$9,$2
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td460 // op2 can be cmp or slt/sltu
655 def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
682 def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
1074 def SelTBteqZSltu: SelT<"bteqz", "sltu">;
1129 def SelTBtneZSltu: SelT<"btnez", "sltu">;
1222 def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIM16Alu>{
1226 def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
1232 def SltuCCRxRy16: FCCRR16_ins<"sltu">;
DMips64InstrInfo.td155 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>, GPR_64;
1219 "sltu\t$rs, $rt, $imm">, GPR_64;
1220 def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
DMicroMipsInstrInfo.td758 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
1408 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;
DMipsSchedule.td330 def II_SLT_SLTU : InstrItinClass; // slt and sltu
DMipsScheduleP5600.td221 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.h269 void sltu(const Operand *OpRd, const Operand *OpRs, const Operand *OpRt);
DIceInstMIPS32.cpp1041 Asm->sltu(getDest(), getSrc(0), getSrc(1)); in emitIAS()
DIceAssemblerMIPS32.cpp1008 void AssemblerMIPS32::sltu(const Operand *OpRd, const Operand *OpRs, in sltu() function in Ice::MIPS32::AssemblerMIPS32
/third_party/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... ra,a6 103 188: 33 30 04 00 sltu zero,s0,zero 104 18c: b3 ...
/third_party/node/deps/v8/src/codegen/loong64/
Dmacro-assembler-loong64.cc713 sltu(rd, rj, rk.rm()); in CallRecordWriteStub()
724 sltu(rd, rj, scratch); in CallRecordWriteStub()
746 sltu(rd, rk.rm(), rj); in CallRecordWriteStub()
754 sltu(rd, scratch, rj); in CallRecordWriteStub()
785 sltu(rd, rk.rm(), rj); in CallRecordWriteStub()
793 sltu(rd, scratch, rj); in CallRecordWriteStub()
Dassembler-loong64.h389 void sltu(Register rd, Register rj, Register rk);
Dassembler-loong64.cc1083 void Assembler::sltu(Register rd, Register rj, Register rk) { in sltu() function in v8::internal::Assembler
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td430 def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
604 // sgt/sgtu are recognised by the GNU assembler but the canonical slt/sltu
738 def : InstAlias<"sltu $rd, $rs1, $imm12",
/third_party/node/deps/v8/src/codegen/riscv64/
Dmacro-assembler-riscv64.cc799 sltu(rd, rs, rt.rm()); in Sltu()
809 sltu(rd, rs, scratch); in Sltu()
830 sltu(rd, rt.rm(), rs); in Sleu()
837 sltu(rd, scratch, rs); in Sleu()
867 sltu(rd, rt.rm(), rs); in Sgtu()
874 sltu(rd, scratch, rs); in Sgtu()
Dassembler-riscv64.h446 void sltu(Register rd, Register rs1, Register rs2);
1068 void snez(Register rd, Register rs) { sltu(rd, zero_reg, rs); } in snez()
/third_party/node/deps/v8/src/codegen/mips/
Dmacro-assembler-mips.cc789 sltu(rd, rs, rt.rm()); in CallRecordWriteStub()
806 sltu(rd, rs, scratch); in CallRecordWriteStub()
828 sltu(rd, rt.rm(), rs); in CallRecordWriteStub()
836 sltu(rd, scratch, rs); in CallRecordWriteStub()
867 sltu(rd, rt.rm(), rs); in CallRecordWriteStub()
875 sltu(rd, scratch, rs); in CallRecordWriteStub()
/third_party/node/deps/v8/src/codegen/mips64/
Dmacro-assembler-mips64.cc922 sltu(rd, rs, rt.rm()); in CallRecordWriteStub()
939 sltu(rd, rs, scratch); in CallRecordWriteStub()
961 sltu(rd, rt.rm(), rs); in CallRecordWriteStub()
969 sltu(rd, scratch, rs); in CallRecordWriteStub()
1000 sltu(rd, rt.rm(), rs); in CallRecordWriteStub()
1008 sltu(rd, scratch, rs); in CallRecordWriteStub()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc5088 "slli.h\006slli.w\004sllv\003slt\004slti\005sltiu\004sltu\003sne\004snei"
7736 …{ 8470 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs,…
7737 …{ 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_…
7738 …{ 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMF…
7739 …{ 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64b…
7740 …{ 8470 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasS…
7741 …{ 8470 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_I…
7742 …{ 8470 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_…
7743 …{ 8470 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMF…
7744 …{ 8470 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64b…
[all …]
/third_party/node/deps/v8/src/builtins/mips/
Dbuiltins-mips.cc3412 __ sltu(v1, t9, a0); // If a0 > t9, don't use next prefetch. in Generate_MemCopyUint8Uint8() local
3578 __ sltu(v1, t9, a0); in Generate_MemCopyUint8Uint8() local
3613 __ sltu(v1, t9, a0); in Generate_MemCopyUint8Uint8() local

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