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Searched refs:spilling (Results 1 – 25 of 58) sorted by relevance

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/third_party/mesa3d/src/freedreno/ir3/
Dir3_spill.c139 bool spilling; member
456 if (ctx->spilling) { in interval_add()
463 if (ctx->spilling) { in interval_add()
483 if (ctx->spilling) { in interval_delete()
489 if (ctx->spilling) { in interval_delete()
545 if (ctx->spilling) { in init_dst()
1043 if (ctx->spilling) { in handle_instr()
1062 if (ctx->spilling) in handle_instr()
1067 if (ctx->spilling) { in handle_instr()
1083 if (ctx->spilling) in handle_instr()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DREADME.txt3 Common register allocation / spilling problem:
109 It's not always a good idea to choose rematerialization over spilling. If all
110 the load / store instructions would be folded then spilling is cheaper because
/third_party/mesa3d/docs/relnotes/
D17.0.5.rst73 - intel/fs: Use regs_written() in spilling cost heuristic for improved
75 - intel/fs: Take into account amount of data read in spilling cost
D19.3.4.rst179 - aco: fix target calculation when vgpr spilling introduces sgpr
180 spilling
D10.5.8.rst39 Register spilling clobbers registers used elsewhere in the shader
D9.1.5.rst79 - ra: Fix register spilling.
D20.1.8.rst75 - pan/mdg: Fix spilling of non-32-bit types
D22.2.2.rst62 - aco/spill: Fix spilling of Phi operands
D22.0.5.rst48 - aco: fix spilling of phis without temp operands
D8.0.1.rst106 - i965/fs: Enable register spilling on gen7 too.
D11.0.7.rst117 - nv50/ir: fix (un)spilling of 3-wide results
D11.1.2.rst117 - nv50/ir: fix memory corruption when spilling and redoing RA
D21.1.4.rst92 - pan/mdg: Fill from TLS before spilling non-SSA nodes
D22.1.1.rst60 - aco: fix spilling of phis without temp operands
D21.1.1.rst75 - aco: fix additional register requirements for spilling
D21.3.8.rst155 - iris: fix register spilling on compute shaders on XeHP
D9.0.2.rst192 - i965/vs: Implement register spilling.
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
Dsfn_docu.txt20 * spilling arrays is broken on Barts and CAYMAN (but it works on Cedar)
/third_party/mesa3d/src/panfrost/ci/
Ddeqp-panfrost-g52.toml44 # Smoke test spilling
/third_party/mesa3d/src/freedreno/ci/
Ddeqp-freedreno-a630-vk.toml42 # force-spilling testing (~10s)
Ddeqp-freedreno-a630.toml149 # spilling testing
/third_party/mesa3d/src/broadcom/compiler/
Dvir_register_allocate.c395 if (c->spilling) { in v3d_setup_spill_base()
546 c->spilling = true; in v3d_spill_reg()
768 c->spilling = false; in v3d_spill_reg()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DREADME-X86-64.txt182 we can change the spilling code to reduce the amount of stack used by half.
/third_party/mesa3d/docs/
Denvvars.rst330 force spilling of all registers in the scalar backend (useful to
331 debug spilling code)
333 force spilling of all registers in the vec4 backend (useful to
334 debug spilling code)
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DREADME-Thumb.txt179 When spilling in thumb mode and the sp offset is too large to fit in the ldr /

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