Home
last modified time | relevance | path

Searched refs:sqtt_flush_bits (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c1053 enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, in gfx10_cs_emit_cache_flush() argument
1065 *sqtt_flush_bits |= RGP_FLUSH_INVAL_ICACHE; in gfx10_cs_emit_cache_flush()
1073 *sqtt_flush_bits |= RGP_FLUSH_INVAL_SMEM_L0; in gfx10_cs_emit_cache_flush()
1078 *sqtt_flush_bits |= RGP_FLUSH_INVAL_VMEM_L0 | RGP_FLUSH_INVAL_L1; in gfx10_cs_emit_cache_flush()
1084 *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2; in gfx10_cs_emit_cache_flush()
1091 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_L2; in gfx10_cs_emit_cache_flush()
1103 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB; in gfx10_cs_emit_cache_flush()
1112 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_DB | RGP_FLUSH_INVAL_DB; in gfx10_cs_emit_cache_flush()
1138 *sqtt_flush_bits |= RGP_FLUSH_PS_PARTIAL_FLUSH; in gfx10_cs_emit_cache_flush()
1143 *sqtt_flush_bits |= RGP_FLUSH_VS_PARTIAL_FLUSH; in gfx10_cs_emit_cache_flush()
[all …]
Dradv_sqtt.c66 enum rgp_flush_bits sqtt_flush_bits = 0; in radv_emit_wait_for_idle() local
75 &sqtt_flush_bits, 0); in radv_emit_wait_for_idle()
Dradv_private.h1509 enum rgp_flush_bits sqtt_flush_bits; member
1693 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va);
Dradv_cmd_buffer.c729 enum rgp_flush_bits sqtt_flush_bits = 0; in radv_ace_internal_cache_flush() local
732 true, flush_bits, &sqtt_flush_bits, 0); in radv_ace_internal_cache_flush()
856 enum rgp_flush_bits sqtt_flush_bits = 0; in radv_cmd_buffer_after_draw() local
865 radv_cmd_buffer_uses_mec(cmd_buffer), flags, &sqtt_flush_bits, in radv_cmd_buffer_after_draw()
873 true, RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0); in radv_cmd_buffer_after_draw()
Dradv_device.c4536 enum rgp_flush_bits sqtt_flush_bits = 0; in radv_update_preamble_cs() local
4609 si_cs_emit_cache_flush(cs, gfx_level, NULL, 0, is_mec, flush_bits, &sqtt_flush_bits, 0); in radv_update_preamble_cs()
/third_party/mesa3d/src/amd/vulkan/layers/
Dradv_sqtt_layer.c232 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_WAIT_ON_EOP_TS) in radv_describe_barrier_end_delayed()
234 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_VS_PARTIAL_FLUSH) in radv_describe_barrier_end_delayed()
236 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_PS_PARTIAL_FLUSH) in radv_describe_barrier_end_delayed()
238 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_CS_PARTIAL_FLUSH) in radv_describe_barrier_end_delayed()
240 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_PFP_SYNC_ME) in radv_describe_barrier_end_delayed()
242 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_SYNC_CP_DMA) in radv_describe_barrier_end_delayed()
244 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_INVAL_VMEM_L0) in radv_describe_barrier_end_delayed()
246 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_INVAL_ICACHE) in radv_describe_barrier_end_delayed()
248 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_INVAL_SMEM_L0) in radv_describe_barrier_end_delayed()
250 if (cmd_buffer->state.sqtt_flush_bits & RGP_FLUSH_FLUSH_L2) in radv_describe_barrier_end_delayed()
[all …]