| /third_party/mesa3d/src/compiler/spirv/ |
| D | vtn_opencl.c | 37 struct vtn_type **src_types,
58 int ntypes, struct vtn_type **src_types, in vtn_opencl_mangle() argument
65 const struct glsl_type *type = src_types[i]->type; in vtn_opencl_mangle()
66 enum vtn_base_type base_type = src_types[i]->base_type; in vtn_opencl_mangle()
67 if (src_types[i]->base_type == vtn_base_type_pointer) { in vtn_opencl_mangle()
69 int address_space = to_llvm_address_space(src_types[i]->storage_class); in vtn_opencl_mangle()
73 type = src_types[i]->deref->type; in vtn_opencl_mangle()
74 base_type = src_types[i]->deref->base_type; in vtn_opencl_mangle()
88 const struct glsl_type *other_type = src_types[j]->base_type == vtn_base_type_pointer ? in vtn_opencl_mangle()
89 src_types[j]->deref->type : src_types[j]->type; in vtn_opencl_mangle()
[all …]
|
| /third_party/mesa3d/src/panfrost/midgard/ |
| D | mir.c | 135 if (ins->dest_type != ins->src_types[i]) return true; in mir_nontrivial_mod()
153 if (ins->dest_type != ins->src_types[1]) in mir_nontrivial_outmod()
313 nir_alu_type_get_type_size(ins->src_types[i])); in mir_bytemask_of_read_components_index()
444 temp = ins->src_types[0]; in mir_flip()
445 ins->src_types[0] = ins->src_types[1]; in mir_flip()
446 ins->src_types[1] = temp; in mir_flip()
|
| D | midgard_emit.c | 82 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); in mir_pack_mod()
86 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) : in mir_pack_mod()
127 bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16; in vector_to_scalar_alu()
128 bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16; in vector_to_scalar_alu()
338 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); in mir_pack_vector_srcs()
371 nir_alu_type_get_type_size(ins->src_types[0]) : in mir_pack_swizzle_ldst()
470 ASSERTED unsigned comp_sz = nir_alu_type_get_type_size(ins->src_types[0]); in midgard_pack_common_store_mask()
612 unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]); in load_store_from_instr()
618 unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]); in load_store_from_instr()
1043 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]); in emit_binary_bundle()
|
| D | midgard_compile.c | 120 i.src_types[0] = T; \
669 ins->src_types[to] = nir_op_infos[instr->op].input_types[i] | bits; in mir_copy_src()
1070 ins.src_types[1] = nir_type_float32; in emit_alu()
1082 ins.src_types[1] = nir_type_float16; in emit_alu()
1092 ins.src_types[1] = ins.src_types[0]; in emit_alu()
1231 ins.src_types[2] = nir_type_uint32; in emit_ubo_read()
1372 .src_types = { 0, 0, 0, type | bitsize }, in emit_atomic()
1384 ins.src_types[2] = type | bitsize; in emit_atomic()
1397 ins.src_types[1] = nir_type_uint64; in emit_atomic()
1404 ins.src_types[2] = nir_type_uint64; in emit_atomic()
[all …]
|
| D | midgard_schedule.c | 237 unsigned sz0 = nir_alu_type_get_type_size(ains->src_types[0]); in mir_is_scalar()
238 unsigned sz1 = nir_alu_type_get_type_size(ains->src_types[1]); in mir_is_scalar()
399 unsigned type_size = nir_alu_type_get_type_size(ins->src_types[src]) / 8; in mir_adjust_constant()
401 unsigned max_comp = mir_components_for_type(ins->src_types[src]); in mir_adjust_constant()
562 if (ins->src_types[0] != ins->src_types[1]) in mir_is_add_2()
1208 branch->src_types[1] = sadd->dest_type; in mir_schedule_alu()
1234 vadd->src_types[0] = nir_type_uint32; in mir_schedule_alu()
1243 vadd->src_types[0] = nir_type_uint32; in mir_schedule_alu()
1519 mov.dest_type = I->src_types[s]; in mir_lower_ldst()
|
| D | midgard_print.c | 123 unsigned sz = nir_alu_type_get_type_size(ins->src_types[src_idx]); in mir_print_embedded_constant()
161 if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) { in mir_print_src()
162 pan_print_alu_type(ins->src_types[c], stdout); in mir_print_src()
|
| D | midgard_address.c | 244 ins->src_types[2] = nir_type_uint | nir_src_bit_size(*offset); in mir_set_offset()
264 ins->src_types[1] = nir_type_uint | bitsize; in mir_set_offset()
275 ins->src_types[2] = nir_type_uint | match.B.def->bit_size; in mir_set_offset()
|
| D | midgard_ra.c | 286 m.src_types[1] = m.dest_type; in mir_lower_special_reads()
438 if (nir_alu_type_get_type_size(ins->src_types[v]) == 64) in mir_is_64()
514 unsigned size = nir_alu_type_get_type_size(ins->src_types[v]); in allocate_registers()
525 unsigned src_size = nir_alu_type_get_type_size(ins->src_types[s]); in allocate_registers()
738 util_logbase2(nir_alu_type_get_type_size(ins->src_types[i]) / 8); in install_registers_instr()
951 st.dest_type = st.src_types[1] = ins->dest_type; in mir_spill_register()
1117 .dest_type = ins->src_types[i], in mir_demote_uniforms()
|
| D | compiler.h | 103 nir_alu_type src_types[MIR_SRC_COUNT]; member
540 .src_types = { 0, nir_type_uint32 }, in v_mov()
596 ins.src_types[0] = nir_type_uint32; in v_load_store_scratch()
|
| D | midgard_derivatives.c | 108 .src_types = { nir_type_float32, nir_type_float32 }, in midgard_emit_derivatives()
|
| D | midgard_opt_perspective.c | 122 .src_types = { nir_type_float32 }, in midgard_opt_combine_projection()
|
| D | mir_promote_uniforms.c | 333 mov.src_types[1] = mov.dest_type; in midgard_promote_uniforms()
|
| /third_party/skia/third_party/externals/tint/src/ast/ |
| D | module_clone_test.cc | 139 std::unordered_set<sem::Type*> src_types; in TEST() local
141 src_types.emplace(src_type); in TEST()
147 ASSERT_EQ(src_types.count(dst_type), 0u); in TEST()
|
| /third_party/skia/third_party/externals/tint/fuzzers/ |
| D | tint_ast_clone_fuzzer.cc | 80 std::unordered_set<tint::sem::Type*> src_types; in LLVMFuzzerTestOneInput() local
82 src_types.emplace(src_type); in LLVMFuzzerTestOneInput()
88 ASSERT_EQ(src_types.count(dst_type), 0u); in LLVMFuzzerTestOneInput()
|
| /third_party/mesa3d/src/panfrost/lib/ |
| D | pan_blend.c | 657 nir_alu_type src_types[] = { src0_type ?: nir_type_float32, src1_type ?: nir_type_float32 }; in GENX() local
660 for (unsigned i = 0; i < ARRAY_SIZE(src_types); ++i) { in GENX()
661 src_types[i] = nir_alu_type_get_base_type(nir_type) | in GENX()
662 nir_alu_type_get_type_size(src_types[i]); in GENX()
667 … glsl_vector_type(nir_get_glsl_base_type_for_nir_type(src_types[0]), 4), in GENX()
672 … glsl_vector_type(nir_get_glsl_base_type_for_nir_type(src_types[1]), 4), in GENX()
688 src_types[i], nir_type, in GENX()
|
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_nir.c | 180 .src_types = (1 << nir_tex_src_coord) | (1 << nir_tex_src_lod) | in si_late_optimize_16bit_samplers()
187 .src_types = (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy), in si_late_optimize_16bit_samplers()
|
| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_mediump.c | 698 if (!(BITFIELD_BIT(tex->src[i].src_type) & options->src_types)) in fold_16bit_tex_srcs()
|
| D | nir.h | 5355 unsigned src_types; member
|
| /third_party/mesa3d/src/freedreno/ir3/ |
| D | ir3_nir.c | 776 .src_types = (1 << nir_tex_src_coord) | in ir3_nir_lower_variant()
|
| /third_party/alsa-utils/alsaloop/ |
| D | pcmjob.c | 56 static const char *src_types[] = { variable
1646 snd_output_printf(loop->output, " (%s)", src_types[loop->src_converter_type]); in pcmjob_start()
|
| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_pipeline.c | 4898 .src_types = (1 << nir_tex_src_coord) | (1 << nir_tex_src_lod) | in radv_create_shaders()
4905 .src_types = (1 << nir_tex_src_ddx) | (1 << nir_tex_src_ddy), in radv_create_shaders()
|
| /third_party/mesa3d/docs/relnotes/ |
| D | 20.1.0.rst | 495 - pan/bi: Fix missing src_types
|
| D | 20.2.0.rst | 409 - pan/mdg: Use src_types to determine size in scheduling
|