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Searched refs:stencil_level (Results 1 – 11 of 11) sorted by relevance

/third_party/libdrm/radeon/
Dradeon_surface.c795 struct radeon_surface_level *stencil_level = in eg_surface_init_1d_miptrees() local
796 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_1d_miptrees()
803 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
805 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_1d_miptrees()
817 struct radeon_surface_level *stencil_level = in eg_surface_init_2d_miptrees() local
818 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_2d_miptrees()
826 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
828 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_2d_miptrees()
1611 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1612 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_1d_miptrees()
[all …]
Dradeon_surface.h137 struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL]; member
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_surface.c167 surf_level_winsys_to_drm(&surf_drm->stencil_level[i], in surf_winsys_to_drm()
168 &surf_ws->u.legacy.zs.stencil_level[i], in surf_winsys_to_drm()
210 surf_level_drm_to_winsys(&surf_ws->u.legacy.zs.stencil_level[i], in surf_drm_to_winsys()
211 &surf_drm->stencil_level[i], in surf_drm_to_winsys()
/third_party/mesa3d/src/amd/common/
Dac_surface.h144 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; member
Dac_surface.c679 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x; in gfx6_compute_level()
693 surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level]; in gfx6_compute_level()
1282 if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x) in gfx6_compute_surface()
1285 surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x; in gfx6_compute_surface()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_texture.c882 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, in r600_print_texture_info()
883 (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4, in r600_print_texture_info()
887 rtex->surface.u.legacy.zs.stencil_level[i].nblk_x, in r600_print_texture_info()
888 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y, in r600_print_texture_info()
889 rtex->surface.u.legacy.zs.stencil_level[i].mode, in r600_print_texture_info()
Devergreen_state.c764 surflevel = tmp->surface.u.legacy.zs.stencil_level; in evergreen_fill_tex_resource_words()
1419 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256; in evergreen_init_depth_surface()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_texture.c889 i, (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256, in si_print_texture_info()
890 (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4, in si_print_texture_info()
893 tex->surface.u.legacy.zs.stencil_level[i].nblk_x, in si_print_texture_info()
894 tex->surface.u.legacy.zs.stencil_level[i].nblk_y, in si_print_texture_info()
895 tex->surface.u.legacy.zs.stencil_level[i].mode, in si_print_texture_info()
Dsi_state.c2766 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B; in si_init_depth_surface()
4613 surflevel = tex->surface.u.legacy.zs.stencil_level; in si_create_sampler_view()
/third_party/mesa3d/src/amd/vulkan/
Dradv_image.c1974 base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->vk.base_mip_level]; in radv_image_view_make_descriptor()
Dradv_device.c6660 level_info = &surf->u.legacy.zs.stencil_level[level]; in radv_initialise_ds_surface()
6663 s_offs += (uint64_t)surf->u.legacy.zs.stencil_level[level].offset_256B * 256; in radv_initialise_ds_surface()