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Searched refs:subregs (Results 1 – 24 of 24) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td21 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
23 RegisterWithSubRegs<n, subregs> {
37 class Rd<bits<5> num, string n, list<Register> subregs,
39 HexagonDoubleReg<num, n, subregs, alt> {
40 let SubRegs = subregs;
58 class Rcc<bits<5> num, string n, list<Register> subregs,
60 HexagonDoubleReg<num, n, subregs, alt> {
61 let SubRegs = subregs;
75 class Rgg<bits<5> num, string n, list<Register> subregs> :
76 HexagonDoubleReg<num, n, subregs> {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td34 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
35 : RegisterWithSubRegs<n, subregs> {
44 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45 : MipsRegWithSubRegs<Enc, n, subregs> {
53 class AFPR<bits<16> Enc, string n, list<Register> subregs>
54 : MipsRegWithSubRegs<Enc, n, subregs> {
59 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
60 : MipsRegWithSubRegs<Enc, n, subregs> {
66 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
67 : MipsRegWithSubRegs<Enc, n, subregs> {
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVERegisterInfo.td21 class R<bits<7> Enc, string n, list<Register> subregs = [],
23 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFRegisterInfo.td24 class Ri<bits<16> Enc, string n, list<Register> subregs>
25 : RegisterWithSubRegs<n, subregs> {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiRegisterInfo.td12 class LanaiReg<bits<5> num, string n, list<Register> subregs = [],
17 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600RegisterInfo.td19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
29 RegisterWithSubRegs<n, subregs> {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.td20 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs,
22 : RegisterWithSubRegs<n, subregs> {
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td35 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
36 let SubRegs = subregs;
44 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
45 let SubRegs = subregs;
51 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
52 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRRegisterInfo.td16 list<Register> subregs = [],
18 : RegisterWithSubRegs<name, subregs>
24 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
119 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
DSystemZInstrInfo.td716 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterInfo.td16 class ARMReg<bits<16> Enc, string n, list<Register> subregs = [],
20 let SubRegs = subregs;
424 // 32-bit SPR subregs).
448 // Subset of QPR that have 32-bit SPR subregs.
454 // Subset of QPR that have DPR_8 and SPR_8 subregs.
DARM.td247 "Loading into D subregs is slow">;
DARMInstrNEON.td2501 // Translate lane numbers from Q registers to D subregs.
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td94 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
96 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86RegisterInfo.td15 class X86Reg<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> {
18 let SubRegs = subregs;
580 // Represents the lower 16 registers that have VEX/legacy encodable subregs.
DX86InstrCompiler.td1303 // For other extloads, use subregs, since the high contents of the register are
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h302 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { in subregs() function
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterScavenging.cpp224 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) in forward()
DMachineVerifier.cpp127 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) in addRegWithSubRegs()
2005 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) { in checkLiveness()
2024 for (const MCPhysReg &SubReg : TRI->subregs(MOP.getReg())) { in checkLiveness()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-subzero/
DCREDITS.TXT243 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td13 class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],
18 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td187 // List "subregs" specifies which registers are sub-registers to this one. This
191 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
192 let SubRegs = subregs;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc331 …{ "slow-load-D-subreg", "Loading into D subregs is slow", ARM::FeatureSlowLoadDSubreg, { { { 0x0UL…