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Searched refs:sys_vars (Results 1 – 3 of 3) sorted by relevance

/third_party/mesa3d/src/intel/perf/
Dintel_perf.c352 perf->sys_vars.slice_mask = devinfo->slice_masks; in compute_topology_builtins()
353 perf->sys_vars.n_eu_slices = devinfo->num_slices; in compute_topology_builtins()
355 perf->sys_vars.n_eu_slice0123 = 0; in compute_topology_builtins()
366 perf->sys_vars.n_eu_slice0123++; in compute_topology_builtins()
372 perf->sys_vars.n_eu_sub_slices += in compute_topology_builtins()
377 perf->sys_vars.n_eus += util_bitcount(devinfo->eu_masks[i]); in compute_topology_builtins()
386 perf->sys_vars.subslice_mask = 0; in compute_topology_builtins()
393 perf->sys_vars.subslice_mask |= 1ULL << (s * bits_per_subslice + ss); in compute_topology_builtins()
415 memset(&perf->sys_vars, 0, sizeof(perf->sys_vars)); in init_oa_sys_vars()
416 perf->sys_vars.gt_min_freq = min_freq_mhz * 1000000; in init_oa_sys_vars()
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Dintel_perf.h367 } sys_vars; member
Dintel_perf_query.c645 uint64_t overflow_period = pow(2, a_counter_in_bits) / (perf_cfg->sys_vars.n_eus * in intel_perf_init_context()
650 overflow_period, overflow_period / 1000000ul, perf_cfg->sys_vars.n_eus); in intel_perf_init_context()