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Searched refs:thrsw (Results 1 – 18 of 18) sorted by relevance

/third_party/mesa3d/src/broadcom/compiler/
Dqpu_schedule.c391 if (inst->sig.thrsw) { in calculate_deps()
1016 merge.sig.thrsw |= b->sig.thrsw; in qpu_merge_inst()
1070 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()
1168 if (inst->sig.thrsw) in choose_instruction_to_schedule()
1642 if (qinst->qpu.sig.thrsw) in qpu_inst_after_thrsw_valid_in_delay_slot()
1790 sig.thrsw = true; in emit_thrsw()
1832 merge_inst->qpu.sig.thrsw = true; in emit_thrsw()
1855 second_inst->qpu.sig.thrsw = true; in emit_thrsw()
1882 if (inst->qpu.sig.thrsw) in qpu_inst_valid_in_branch_delay_slot()
2291 if (inst->sig.thrsw) { in schedule_instructions()
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Dvir_opt_redundant_flags.c116 if (inst->qpu.sig.thrsw) in vir_opt_redundant_flags_block()
Dqpu_validate.c236 if (inst->sig.thrsw) { in qpu_validate_inst()
Dvir_dump.c220 if (sig->thrsw) in vir_dump_sig()
Dnir_to_vir.c164 c->last_thrsw->qpu.sig.thrsw = true; in vir_emit_thrsw()
4457 if (inst->qpu.sig.thrsw) in vir_remove_thrsw()
4534 struct qinst *thrsw, in vir_restore_last_thrsw() argument
4539 c->last_thrsw = thrsw; in vir_restore_last_thrsw()
Dvir_register_allocate.c1062 if (inst->qpu.sig.thrsw) { in update_graph_and_reg_classes_for_inst()
Dvir.c84 inst->qpu.sig.thrsw) { in vir_has_side_effects()
/third_party/mesa3d/src/broadcom/qpu/
Dqpu_disasm.c206 if (!sig->thrsw && in v3d_qpu_disasm_sig()
222 if (sig->thrsw) in v3d_qpu_disasm_sig()
Dqpu_instr.h43 bool thrsw:1; member
Dqpu_pack.c107 #define THRSW .thrsw = true
/third_party/mesa3d/docs/relnotes/
D18.2.8.rst80 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
D18.3.2.rst137 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
D21.2.2.rst190 - broadcom/compiler: force a last thrsw for spilling
D19.0.0.rst755 - v3d: Make sure that a thrsw doesn't split a multop from its umul24.
869 - v3d: Fix the check for "is the last thrsw inside control flow"
D19.1.0.rst1391 - v3d: Fix the check for "is the last thrsw inside control flow"
1470 - v3d: Fix an invalid reuse of flags generation from before a thrsw.
D22.0.0.rst1662 - broadcom/compiler: disallow tsy barrier in thrsw delay slots
1687 - broadcom/compiler: improve thrsw merge
D21.3.0.rst2310 - broadcom/compiler: force a last thrsw for spilling
D21.1.0.rst2354 - broadcom/compiler: try to fill up delay slots after a thrsw