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Searched refs:v16f32 (Results 1 – 25 of 26) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h131 v16f32 = 76, // 16 x f32 enumerator
367 return (SimpleTy == MVT::v32f16 || SimpleTy == MVT::v16f32 || in is512BitVector()
523 case v16f32: in getVectorElementType()
591 case v16f32: in getVectorNumElements()
796 case v16f32: in getSizeInBits()
999 if (NumElements == 16) return MVT::v16f32; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td83 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
94 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
132 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>;
139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
148 defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, sub_xmm>;
155 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32, sub_ymm>;
DX86TargetTransformInfo.cpp547 { ISD::FADD, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
548 { ISD::FSUB, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
549 { ISD::FMUL, MVT::v16f32, 1 }, // Skylake from http://www.agner.org/ in getArithmeticInstrCost()
1034 {TTI::SK_Broadcast, MVT::v16f32, 1}, // vbroadcastps in getShuffleCost()
1039 {TTI::SK_Reverse, MVT::v16f32, 1}, // vpermps in getShuffleCost()
1046 {TTI::SK_PermuteSingleSrc, MVT::v16f32, 1}, // vpermps in getShuffleCost()
1058 {TTI::SK_PermuteTwoSrc, MVT::v16f32, 1}, // vpermt2ps in getShuffleCost()
1337 { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 }, in getCastInstrCost()
1360 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1362 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
[all …]
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrFragmentsSIMD.td808 def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
865 (v16f32 (alignedload node:$ptr))>;
1003 def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
DX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86InstrAVX512.td420 def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
932 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
934 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
961 def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 4))),
963 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
1479 def : Pat<(v16f32 (X86SubVBroadcast (loadv8f32 addr:$src))),
1493 def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))),
1494 (VINSERTF64x4Zrr (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm),
1521 (v16f32 immAllZerosV)),
1537 (bc_v8f64 (v16f32 (X86SubVBroadcast (loadv8f32 addr:$src)))),
[all …]
DX86ISelLowering.cpp755 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, in X86TargetLowering()
1447 addRegisterClass(MVT::v16f32, &X86::VR512RegClass); in X86TargetLowering()
1459 for (MVT VT : { MVT::v16f32, MVT::v8f64 }) { in X86TargetLowering()
1482 setOperationAction(ISD::STRICT_FADD, MVT::v16f32, Legal); in X86TargetLowering()
1484 setOperationAction(ISD::STRICT_FSUB, MVT::v16f32, Legal); in X86TargetLowering()
1486 setOperationAction(ISD::STRICT_FMUL, MVT::v16f32, Legal); in X86TargetLowering()
1488 setOperationAction(ISD::STRICT_FDIV, MVT::v16f32, Legal); in X86TargetLowering()
1490 setOperationAction(ISD::STRICT_FSQRT, MVT::v16f32, Legal); in X86TargetLowering()
1526 for (auto VT : { MVT::v16f32, MVT::v8f64 }) { in X86TargetLowering()
1549 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom); in X86TargetLowering()
[all …]
DX86FastISel.cpp440 case MVT::v16f32: in X86FastEmitLoad()
612 case MVT::v16f32: in X86FastEmitStore()
DX86InstrCompiler.td652 def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, timm:$cond, EFLAGS)),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp262 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
263 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
264 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
265 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
289 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
290 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 } in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td564 def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
569 def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
574 def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
640 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
671 def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
DAMDGPUCallingConv.td126 CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
DSIInstructions.td921 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
924 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index)
1054 def : BitConvert <v16i32, v16f32, VReg_512>;
1055 def : BitConvert <v16f32, v16i32, VReg_512>;
1423 defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">;
DSIInstrInfo.td2306 def VOP_V16F32_F32_F32_V16F32 : VOPProfile <[v16f32, f32, f32, v16f32]>;
2309 def VOP_V16F32_V4F16_V4F16_V16F32 : VOPProfile <[v16f32, v4f16, v4f16, v16f32]>;
2312 def VOP_V16F32_V2I16_V2I16_V16F32 : VOPProfile <[v16f32, v2i16, v2i16, v16f32]>;
DAMDGPUISelLowering.cpp88 setOperationAction(ISD::LOAD, MVT::v16f32, Promote); in AMDGPUTargetLowering()
89 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
157 setLoadExtAction(ISD::EXTLOAD, MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
188 setOperationAction(ISD::STORE, MVT::v16f32, Promote); in AMDGPUTargetLowering()
189 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32); in AMDGPUTargetLowering()
221 setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand); in AMDGPUTargetLowering()
296 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16f32, Custom); in AMDGPUTargetLowering()
DSMInstructions.td821 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16f32>;
DSIISelLowering.cpp148 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); in SITargetLowering()
261 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, in SITargetLowering()
310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
5192 Type = MVT::v16f32; in getBuildDwordsVector()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc253 if (LocVT == MVT::v16f32 ||
934 LocVT == MVT::v16f32 ||
1021 LocVT == MVT::v16f32 ||
1150 LocVT == MVT::v16f32 ||
1206 LocVT == MVT::v16f32 ||
1270 LocVT == MVT::v16f32 ||
1583 LocVT == MVT::v16f32 ||
1641 LocVT == MVT::v16f32 ||
1718 LocVT == MVT::v16f32 ||
2006 LocVT == MVT::v16f32 ||
[all …]
DX86GenFastISel.inc1173 if (RetVT.SimpleTy != MVT::v16f32)
1224 case MVT::v16f32: return fastEmit_ISD_FSQRT_MVT_v16f32_r(RetVT, Op0, Op0IsKill);
1812 if (RetVT.SimpleTy != MVT::v16f32)
2148 if (RetVT.SimpleTy != MVT::v16f32)
2199 case MVT::v16f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v16f32_r(RetVT, Op0, Op0IsKill);
2310 if (RetVT.SimpleTy != MVT::v16f32)
2432 if (RetVT.SimpleTy != MVT::v16f32)
2698 if (RetVT.SimpleTy != MVT::v16f32)
3182 case MVT::v16f32: return fastEmit_X86ISD_CVTNEPS2BF16_MVT_v16f32_r(RetVT, Op0, Op0IsKill);
3338 case MVT::v16f32: return fastEmit_X86ISD_CVTP2SI_MVT_v16f32_r(RetVT, Op0, Op0IsKill);
[all …]
DX86GenGlobalISel.inc13064 …{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VADDPSZrr:{ *:[v16f32
13385 …{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VSUBPSZrr:{ *:[v16f32
13706 …{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VMULPSZrr:{ *:[v16f32
14027 …{ *:[v16f32] } VR512:{ *:[v16f32] }:$src1, VR512:{ *:[v16f32] }:$src2) => (VDIVPSZrr:{ *:[v16f32
14924 …// (sint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTDQ2PSZrr:{ *:[v16f32] } VR512:{…
15146 …// (uint_to_fp:{ *:[v16f32] } VR512:{ *:[v16i32] }:$src) => (VCVTUDQ2PSZrr:{ *:[v16f32] } VR512:…
17130 …// (fsqrt:{ *:[v16f32] } VR512:{ *:[v16f32] }:$src) => (VSQRTPSZr:{ *:[v16f32] } VR512:{ *:[v16f…
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp354 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
355 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 21 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td103 def v16f32 : ValueType<512, 76>; // 16 x f32 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp221 case MVT::v16f32: return VectorType::get(Type::getFloatTy(Context), 16); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td281 def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float

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