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Searched refs:v16i32 (Results 1 – 25 of 36) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td82 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
131 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>;
132 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
134 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>;
135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
138 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>;
139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
[all …]
DX86TargetTransformInfo.cpp369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
525 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
526 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
527 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) in getArithmeticInstrCost()
1036 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd in getShuffleCost()
1041 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd in getShuffleCost()
[all …]
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
747 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
DX86InstrAVX512.td54 // Size of the element type in bits, e.g. 32 for v16i32.
411 [(set VR512:$dst, (v16i32 immAllZerosV))]>;
413 [(set VR512:$dst, (v16i32 immAllOnesV))]>;
431 (v16i32 immAllOnesV),
432 (v16i32 immAllZerosV)))]>;
928 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
930 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
957 def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 4))),
959 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
1401 def : Pat<(v16i32 (X86VBroadcast (loadi32 addr:$src))),
[all …]
DX86InstrFragmentsSIMD.td811 def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
871 (v16i32 (alignedload node:$ptr))>;
943 return Mgt->getIndex().getValueType() == MVT::v16i32;
978 return Sc->getIndex().getValueType() == MVT::v16i32;
1000 def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
DX86ISelLowering.cpp1216 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1218 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1446 addRegisterClass(MVT::v16i32, &X86::VR512RegClass); in X86TargetLowering()
1452 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i8, Legal); in X86TargetLowering()
1453 setLoadExtAction(ExtType, MVT::v16i32, MVT::v16i16, Legal); in X86TargetLowering()
1468 setOperationPromotedToType(ISD::FP_TO_SINT , VT, MVT::v16i32); in X86TargetLowering()
1469 setOperationPromotedToType(ISD::FP_TO_UINT , VT, MVT::v16i32); in X86TargetLowering()
1470 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, VT, MVT::v16i32); in X86TargetLowering()
1471 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, VT, MVT::v16i32); in X86TargetLowering()
1473 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering()
[all …]
DX86RegisterInfo.td577 def VR512 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
581 def VR512_0_15 : RegisterClass<"X86", [v16f32, v8f64, v64i8, v32i16, v16i32, v8i64],
DX86ISelDAGToDAG.cpp4041 case MVT::v16i32: in getVPTESTMOpc()
4059 case MVT::v16i32: in getVPTESTMOpc()
4088 case MVT::v16i32: in getVPTESTMOpc()
4118 case MVT::v16i32: in getVPTESTMOpc()
4136 case MVT::v16i32: in getVPTESTMOpc()
4165 case MVT::v16i32: in getVPTESTMOpc()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td85 CCIfType<[v16i32,v32i16,v64i8],
91 CCIfType<[v16i32,v32i16,v64i8],
117 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsics.td263 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
264 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
267 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
268 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
280 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
281 (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
292 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
293 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
331 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>,
336 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
67 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1),
72 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
DHexagonRegisterInfo.td292 [v16i32, v32i32, v16i32]>;
DHexagonISelLoweringHVX.cpp16 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
27 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
198 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) in initializeHVXLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h98 v16i32 = 49, // 16 x i32 enumerator
370 SimpleTy == MVT::v16i32 || SimpleTy == MVT::v8i64); in is512BitVector()
481 case v16i32: in getVectorElementType()
588 case v16i32: in getVectorNumElements()
793 case v16i32: in getSizeInBits()
964 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
322 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
323 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
611 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 }, in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp235 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
236 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
239 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
264 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
265 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td564 def SGPR_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
569 def TTMP_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
574 def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
640 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
671 def AReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32,
DAMDGPUCallingConv.td126 CCIfType<[v16i32, v16f32], CCAssignToStack<64, 4>>
DSIInstructions.td914 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
917 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index)
1054 def : BitConvert <v16i32, v16f32, VReg_512>;
1055 def : BitConvert <v16f32, v16i32, VReg_512>;
1428 defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">;
DSMInstructions.td809 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
815 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16i32>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc255 LocVT == MVT::v16i32 ||
932 LocVT == MVT::v16i32 ||
1019 LocVT == MVT::v16i32 ||
1148 LocVT == MVT::v16i32 ||
1204 LocVT == MVT::v16i32 ||
1268 LocVT == MVT::v16i32 ||
1581 LocVT == MVT::v16i32 ||
1639 LocVT == MVT::v16i32 ||
1716 LocVT == MVT::v16i32 ||
2004 LocVT == MVT::v16i32 ||
[all …]
DX86GenGlobalISel.inc1547 …{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPADDDZrr:{ *:[v16i32…
2091 …{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPSUBDZrr:{ *:[v16i32…
2518 …{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPMULLDZrr:{ *:[v16i3…
3896 …{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPANDDZrr:{ *:[v16i32…
5470 …:{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPORDZrr:{ *:[v16i32…
6792 …{ *:[v16i32] } VR512:{ *:[v16i32] }:$src1, VR512:{ *:[v16i32] }:$src2) => (VPXORDZrr:{ *:[v16i32…
10555 …K16:{ *:[v16i1] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1…
10587 …16:{ *:[v16i1] }:$src) => (VPMOVDWZrr:{ *:[v16i16] } (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i1…
10610 …// (anyext:{ *:[v16i32] } VK16:{ *:[v16i1] }:$src) => (VPMOVM2DZrr:{ *:[v16i32] } VK16:{ *:[v16i…
10772 …// (trunc:{ *:[v16i8] } VR512:{ *:[v16i32] }:$src) => (VPMOVDBZrr:{ *:[v16i8] } VR512:{ *:[v16i3…
[all …]
DX86GenFastISel.inc142 if (RetVT.SimpleTy != MVT::v16i32)
187 case MVT::v16i32: return fastEmit_ISD_ABS_MVT_v16i32_r(RetVT, Op0, Op0IsKill);
289 case MVT::v16i32: return fastEmit_ISD_ANY_EXTEND_MVT_v16i1_MVT_v16i32_r(Op0, Op0IsKill);
567 if (RetVT.SimpleTy != MVT::v16i32)
609 case MVT::v16i32: return fastEmit_ISD_CTLZ_MVT_v16i32_r(RetVT, Op0, Op0IsKill);
719 if (RetVT.SimpleTy != MVT::v16i32)
767 case MVT::v16i32: return fastEmit_ISD_CTPOP_MVT_v16i32_r(RetVT, Op0, Op0IsKill);
1414 case MVT::v16i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i1_MVT_v16i32_r(Op0, Op0IsKill);
1470 case MVT::v16i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v16i8_MVT_v16i32_r(Op0, Op0IsKill);
1510 if (RetVT.SimpleTy != MVT::v16i32)
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td73 def v16i32 : ValueType<512, 49>; // 16 x i32 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp194 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16); in getTypeForEVT()

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