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Searched refs:v1f64 (Results 1 – 15 of 15) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3200 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3227 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3254 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3281 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3308 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3335 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3362 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3389 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3416 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3437 VT == MVT::v1f64) { in Select()
[all …]
DAArch64InstrInfo.td2142 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
2285 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2469 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2804 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2882 def : Pat<(store (v1f64 FPR64:$Rt),
3016 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
3164 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
3218 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
3428 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
3484 def : Pat<(v1f64 (fmaximum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
[all …]
DAArch64CallingConvention.td109 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
118 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
226 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
242 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
263 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
285 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
DAArch64ISelLowering.cpp154 addDRTypeForNEON(MVT::v1f64); in AArch64TargetLowering()
705 setOperationAction(ISD::FABS, MVT::v1f64, Expand); in AArch64TargetLowering()
706 setOperationAction(ISD::FADD, MVT::v1f64, Expand); in AArch64TargetLowering()
707 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
708 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand); in AArch64TargetLowering()
709 setOperationAction(ISD::FCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
710 setOperationAction(ISD::FDIV, MVT::v1f64, Expand); in AArch64TargetLowering()
711 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand); in AArch64TargetLowering()
712 setOperationAction(ISD::FMA, MVT::v1f64, Expand); in AArch64TargetLowering()
713 setOperationAction(ISD::FMUL, MVT::v1f64, Expand); in AArch64TargetLowering()
[all …]
DAArch64RegisterInfo.td429 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
DAArch64InstrFormats.td6594 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6611 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6768 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h139 v1f64 = 84, // 1 x f64 enumerator
345 SimpleTy == MVT::v2f32 || SimpleTy == MVT::v1f64); in is64BitVector()
536 case v1f64: in getVectorElementType()
659 case v1f64: in getVectorNumElements()
744 case v1f64: return TypeSize::Fixed(64); in getSizeInBits()
1009 if (NumElements == 1) return MVT::v1f64; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc309 LocVT == MVT::v1f64 ||
359 LocVT == MVT::v1f64 ||
553 LocVT == MVT::v1f64 ||
620 LocVT == MVT::v1f64 ||
708 LocVT == MVT::v1f64 ||
790 LocVT == MVT::v1f64 ||
1122 LocVT == MVT::v1f64 ||
DAArch64GenGlobalISel.inc7019 …[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] })) => (INSERT_SUBREG:{ *:[v2f64] } (IMPLICI…
7078 …v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn) => (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (…
9261 …// (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f6…
9376 …// (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn) => (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *…
9416 …// (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn) => (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f6…
9551 // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[v1i64] }:$src
9715 // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src) => FPR64:{ *:[f64] }:$src
9729 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src) => FPR64:{ *:[v1f64] }:$src
9743 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src) => FPR64:{ *:[v1f64] }:$src
9757 // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src) => FPR64:{ *:[v1f64] }:$src
[all …]
DAArch64GenFastISel.inc746 case MVT::v1f64: return fastEmit_AArch64ISD_FCMEQz_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
814 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
882 case MVT::v1f64: return fastEmit_AArch64ISD_FCMGTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
950 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLEz_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
1018 case MVT::v1f64: return fastEmit_AArch64ISD_FCMLTz_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
1051 if (RetVT.SimpleTy != MVT::v1f64)
1068 case MVT::v1f64: return fastEmit_AArch64ISD_FRECPE_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
1101 if (RetVT.SimpleTy != MVT::v1f64)
1118 case MVT::v1f64: return fastEmit_AArch64ISD_FRSQRTE_MVT_v1f64_r(RetVT, Op0, Op0IsKill);
1987 case MVT::v1f64: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v1f64_r(Op0, Op0IsKill);
[all …]
DAArch64GenRegisterInfo.inc5183 …/* 7 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64,…
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td111 def v1f64 : ValueType<64, 84>; // 1 x f64 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp229 case MVT::v1f64: return VectorType::get(Type::getDoubleTy(Context), 1); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td283 def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2733 case MVT::v1f64: in SelectVLDDup()