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Searched refs:v2i32 (Results 1 – 25 of 83) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc1219 /* 2581*/ OPC_SwitchType /*2 cases */, 19, MVT::v2i32,// ->2603
1224 MVT::v2i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
1225 …v2i32] } (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{ *:[v2i32] } DPR:…
1226 … // Dst: (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1274 /* 2700*/ OPC_CheckType, MVT::v2i32,
1279 MVT::v2i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
1280 …v2i32] } (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{ *:[v2i32] } DPR:…
1281 … // Dst: (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1302 /* 2753*/ OPC_CheckType, MVT::v2i32,
1307 MVT::v2i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
[all …]
DARMGenGlobalISel.inc1651 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i3…
1676 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i3…
1701 …v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2…
1726 …v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2…
1749 …v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1…
1772 …v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)…
1789 …// (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } …
1825 …v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src…
1854 …v2i32] } 1663:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src…
1883 …v2i32] } 1662:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:…
[all …]
DARMGenFastISel.inc351 case MVT::v2i32: return fastEmit_ARMISD_VDUP_MVT_i32_MVT_v2i32_r(Op0, Op0IsKill);
571 if (RetVT.SimpleTy != MVT::v2i32)
639 case MVT::v2i32: return fastEmit_ARMISD_VREV64_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
709 if (RetVT.SimpleTy != MVT::v2i32)
735 case MVT::v2i32: return fastEmit_ISD_ABS_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
774 case MVT::v2i32: return fastEmit_ISD_ANY_EXTEND_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
838 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_f64_MVT_v2i32_r(Op0, Op0IsKill);
891 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v8i8_MVT_v2i32_r(Op0, Op0IsKill);
1010 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v4i16_MVT_v2i32_r(Op0, Op0IsKill);
1224 case MVT::v2i32: return fastEmit_ISD_BITCAST_MVT_v1i64_MVT_v2i32_r(Op0, Op0IsKill);
[all …]
DARMGenCallingConv.inc64 LocVT == MVT::v2i32 ||
234 LocVT == MVT::v2i32 ||
353 LocVT == MVT::v2i32 ||
420 LocVT == MVT::v2i32 ||
514 LocVT == MVT::v2i32 ||
602 LocVT == MVT::v2i32 ||
705 LocVT == MVT::v2i32 ||
819 LocVT == MVT::v2i32 ||
876 LocVT == MVT::v2i32 ||
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td590 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|GE|GT)(32|64|v2f32|v2i32)$")>;
591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
600 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVTZ(S|U)v2i32(_shift)?$")>;
643 (instregex "^ML(A|S)(v8i8|v4i16|v2i32)(_indexed)?$")>;
658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
661 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIC|ORR)(v2i32|v4i16)$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
665 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)(ADDLP|HADD|HSUB|SHL)(v2i32|v4i16|v8i8)(_v.…
667 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^(S|U)SHR(v2i32|v4i16|v8i8)_shift$")>;
[all …]
DAArch64TargetTransformInfo.cpp326 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
329 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
360 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
363 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
367 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
370 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
389 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
392 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
966 { TTI::SK_Broadcast, MVT::v2i32, 1 }, in getShuffleCost()
978 { TTI::SK_Transpose, MVT::v2i32, 1 }, in getShuffleCost()
[all …]
DAArch64CallingConvention.td31 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
36 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
109 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
118 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
127 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
135 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v8i8],
151 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
188 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
226 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16],
242 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16],
[all …]
DAArch64SchedKryoDetails.td19 (instregex "(S|U)R?SRA(d|(v2i32|v4i16|v8i8)_shift)")>;
33 (instregex "(S|U)ABA(v8i8|v4i16|v2i32)")>;
57 (instregex "(S|U)(ABD|RHADD)(v8i8|v4i16|v2i32)")>;
69 (instregex "(S|U)ADALP(v8i8|v4i16|v2i32)_v.*")>;
87 (instregex "((S|U)ADDLP|ABS)(v2i32|v4i16|v8i8)(_v.*)?")>;
147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
171 (instregex "((S|U)H(ADD|SUB)|ADDP)(v8i8|v4i16|v2i32)")>;
201 (instregex "^(S|U)QADD(v8i8|v4i16|v2i32)")>;
219 (instregex "(S|U)QSHLU?(d|s|h|b|(v8i8|v4i16|v2i32)_shift)$")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
[all …]
DAArch64ISelDAGToDAG.cpp610 case MVT::v2i32: in tryMLAV64LaneV128()
3194 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3221 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3248 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3275 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3302 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3329 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3356 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3383 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
3410 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { in Select()
[all …]
DAArch64SchedA57.td345 // D form - v8i8, v4i16, v2i32
353 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]ABA(v8i8|v4i16|v2i32)$")>;
360 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
379 def : InstRW<[A57Write_5cyc_1W], (instregex "^ML[AS](v8i8|v4i16|v2i32)(_indexed)?$")>;
410 …7Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
424 // D form - v2i32
433 def : InstRW<[A57Write_5cyc_1V], (instregex "^FADDP(v2f32|32|64|v2i32)")>;
438 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
445 def : InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i6…
[all …]
DAArch64InstrInfo.td2098 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
2134 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
2255 def : Pat <(v2i32 (scalar_to_vector (i32
2257 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
2280 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2460 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
2796 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
2897 def : Pat<(store (v2i32 FPR64:$Rt),
3034 def : Pat<(store (v2i32 FPR64:$Rt),
3158 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
[all …]
DAArch64InstrFormats.td5160 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64,
5162 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5176 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
5177 (!cast<Instruction>(inst#"v2i32") V64:$LHS, V64:$RHS)>;
5204 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b101, opc, V64,
5206 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
5230 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b101, opc, V64,
5232 [(set (v2i32 V64:$dst),
5233 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5287 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp221 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
222 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
250 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
251 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
275 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
276 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
282 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
283 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, in getCastInstrCost()
285 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
286 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
DARMInstrNEON.td1071 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1098 def : Pat<(insert_subvector undef, (v2i32 DPR:$src), (i32 0)),
1384 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
2135 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2185 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
3327 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3330 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2i32 DPR:$Vm), fc)))]>;
3334 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
3410 def v2i32 : N3VD_cmp<op24, op23, 0b10, op11_8, op4, itinD32,
3412 v2i32, v2i32, fc, Commutable>;
[all …]
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
185 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
211 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
233 CCIfType<[v1i64, v2i32, v4i16, v4f16, v8i8, v2f32], CCBitConvertToType<f64>>,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td17 CCIfType<[i64,v2i32,v4i16,v8i8],
43 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCIfType<[i64,v2i32,v4i16,v8i8],
69 CCIfType<[i64,v2i32,v4i16,v8i8],
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DCaymanInstructions.td84 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>;
188 def : R600Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)),
202 def : R600Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)),
216 def : R600Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)),
DAMDGPUISelLowering.cpp74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
95 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
101 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
174 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); in AMDGPUTargetLowering()
201 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32); in AMDGPUTargetLowering()
214 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand); in AMDGPUTargetLowering()
287 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
357 MVT::v2i32, MVT::v3i32, MVT::v4i32, MVT::v5i32 in AMDGPUTargetLowering()
439 AddPromotedToType(ISD::SELECT, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp235 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32); in tryInlineAsm()
239 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32, in tryInlineAsm()
268 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32, in tryInlineAsm()
282 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32); in tryInlineAsm()
DSparcCallingConv.td24 // As are v2i32 arguments (this would be the default behavior for
25 // v2i32 if it wasn't allocated to the IntPair register-class)
26 CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Split_64">>,
37 CCIfType<[v2i32], CCCustom<"CC_Sparc_Assign_Ret_Split_64">>
DSparcISelLowering.cpp240 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32); in LowerFormalArguments_32()
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
858 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
989 if (RVLocs[i].getLocVT() == MVT::v2i32) { in LowerCall_32()
990 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()
1433 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass); in SparcTargetLowering()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1790 …:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (SADALPv2i32_v1i64:{ *:[v1i64] } V6…
1811 …:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd) => (UADALPv2i32_v1i64:{ *:[v1i64] } V6…
1832 …] } 371:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64…
1853 …] } 429:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)) => (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64…
1904 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32…
1927 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32…
1948 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 371:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i3…
1968 …v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 429:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i3…
1990 …v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 370:{ *:[iPTR] }, V64:{ *:[v2i32…
2013 …v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 428:{ *:[iPTR] }, V64:{ *:[v2i32…
[all …]
DAArch64GenCallingConv.inc51 LocVT = MVT::v2i32;
62 if (LocVT == MVT::v2i32 ||
306 LocVT == MVT::v2i32 ||
362 LocVT == MVT::v2i32 ||
398 LocVT = MVT::v2i32;
550 LocVT == MVT::v2i32 ||
623 LocVT == MVT::v2i32 ||
653 LocVT = MVT::v2i32;
705 LocVT == MVT::v2i32 ||
742 LocVT = MVT::v2i32;
[all …]
DAArch64GenFastISel.inc173 if (RetVT.SimpleTy != MVT::v2i32)
214 case MVT::v2i32: return fastEmit_AArch64ISD_CMEQz_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
261 if (RetVT.SimpleTy != MVT::v2i32)
302 case MVT::v2i32: return fastEmit_AArch64ISD_CMGEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
349 if (RetVT.SimpleTy != MVT::v2i32)
390 case MVT::v2i32: return fastEmit_AArch64ISD_CMGTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
437 if (RetVT.SimpleTy != MVT::v2i32)
478 case MVT::v2i32: return fastEmit_AArch64ISD_CMLEz_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
525 if (RetVT.SimpleTy != MVT::v2i32)
566 case MVT::v2i32: return fastEmit_AArch64ISD_CMLTz_MVT_v2i32_r(RetVT, Op0, Op0IsKill);
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h93 v2i32 = 44, // 2 x i32 enumerator
343 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || in is64BitVector()
476 case v2i32: in getVectorElementType()
639 case v2i32: in getVectorNumElements()
740 case v2i32: in getSizeInBits()
959 if (NumElements == 2) return MVT::v2i32; in getVectorVT()

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