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Searched refs:v32i8 (Results 1 – 24 of 24) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp317 { ISD::SHL, MVT::v32i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
318 { ISD::SRL, MVT::v32i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
319 { ISD::SRA, MVT::v32i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
336 { ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split. in getArithmeticInstrCost()
337 { ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split. in getArithmeticInstrCost()
338 { ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split. in getArithmeticInstrCost()
384 { ISD::SDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
386 { ISD::UDIV, MVT::v32i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
387 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
DX86CallingConv.td115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
538 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrVecCompiler.td76 defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>;
98 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
120 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>;
129 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32, sub_xmm>;
143 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>;
159 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>;
DX86InstrSSE.td158 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
564 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
572 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
2299 def : Pat<(v32i8 (and VR256:$src1, VR256:$src2)),
2306 def : Pat<(v32i8 (or VR256:$src1, VR256:$src2)),
2313 def : Pat<(v32i8 (xor VR256:$src1, VR256:$src2)),
2320 def : Pat<(v32i8 (X86andnp VR256:$src1, VR256:$src2)),
2359 def : Pat<(v32i8 (and VR256:$src1, VR256:$src2)),
2368 def : Pat<(v32i8 (or VR256:$src1, VR256:$src2)),
2377 def : Pat<(v32i8 (xor VR256:$src1, VR256:$src2)),
[all …]
DX86ISelLowering.cpp1134 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1142 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1149 addRegisterClass(MVT::v32i8, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1208 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1225 setOperationAction(ISD::ROTL, MVT::v32i8, Custom); in X86TargetLowering()
1231 setOperationAction(ISD::SELECT, MVT::v32i8, Custom); in X86TargetLowering()
1243 setOperationAction(ISD::BITREVERSE, MVT::v32i8, Custom); in X86TargetLowering()
1245 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1266 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1274 setOperationAction(ISD::MUL, MVT::v32i8, Custom); in X86TargetLowering()
[all …]
DX86InstrFragmentsSIMD.td805 def loadv32i8 : PatFrag<(ops node:$ptr), (v32i8 (load node:$ptr))>;
861 (v32i8 (alignedload node:$ptr))>;
990 def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
DX86RegisterInfo.td559 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
592 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86InstrAVX512.td454 def : Pat<(v32i8 immAllZerosV), (AVX512_256_SET0)>;
942 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
971 (v32i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_ymm)),
1505 def : Pat<(v64i8 (X86SubVBroadcast (v32i8 VR256X:$src))),
1507 (v32i8 VR256X:$src), 1)>;
1568 def : Pat<(v32i8 (X86SubVBroadcast (loadv16i8 addr:$src))),
1607 def : Pat<(v32i8 (X86SubVBroadcast (v16i8 VR128X:$src))),
1608 (VINSERTI32x4Z256rr (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
3799 def : Pat<(alignedstore (v32i8 VR256X:$src), addr:$dst),
3805 def : Pat<(store (v32i8 VR256X:$src), addr:$dst),
[all …]
DX86ISelDAGToDAG.cpp4029 case MVT::v32i8: in getVPTESTMOpc()
4076 case MVT::v32i8: in getVPTESTMOpc()
4106 case MVT::v32i8: in getVPTESTMOpc()
4153 case MVT::v32i8: in getVPTESTMOpc()
DX86InstrXOP.td395 def : Pat<(v32i8 (or (and VR256:$src3, VR256:$src1),
DX86FastISel.cpp429 case MVT::v32i8: in X86FastEmitLoad()
602 case MVT::v32i8: in X86FastEmitStore()
DX86InstrCompiler.td611 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, timm:$cond, EFLAGS)),
634 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, timm:$cond, EFLAGS)),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h77 v32i8 = 30, // 32 x i8 enumerator
360 SimpleTy == MVT::v4f64 || SimpleTy == MVT::v32i8 || in is256BitVector()
450 case v32i8: in getVectorElementType()
574 case v32i8: in getVectorNumElements()
777 case v32i8: in getSizeInBits()
941 if (NumElements == 32) return MVT::v32i8; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1563 …dd:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPADDBYrr:{ *:[v32i8]…
1574 …{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPADDBZ256rr:{ *:[v32i…
2107 …ub:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPSUBBYrr:{ *:[v32i8]…
2118 …{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPSUBBZ256rr:{ *:[v32i…
3927 …and:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPANDYrr:{ *:[v32i8]…
3938 …nd:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VANDPSYrr:{ *:[v32i8]…
3949 …{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPANDQZ256rr:{ *:[v32i…
5501 …(or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VPORYrr:{ *:[v32i8] …
5512 …(or:{ *:[v32i8] } VR256:{ *:[v32i8] }:$src1, VR256:{ *:[v32i8] }:$src2) => (VORPSYrr:{ *:[v32i8]…
5523 …{ *:[v32i8] } VR256X:{ *:[v32i8] }:$src1, VR256X:{ *:[v32i8] }:$src2) => (VPORQZ256rr:{ *:[v32i8…
[all …]
DX86GenCallingConv.inc522 LocVT = MVT::v32i8;
913 if (LocVT == MVT::v32i8 ||
1006 if (LocVT == MVT::v32i8 ||
1135 if (LocVT == MVT::v32i8 ||
1183 if (LocVT == MVT::v32i8 ||
1247 if (LocVT == MVT::v32i8 ||
1520 LocVT = MVT::v32i8;
1560 if (LocVT == MVT::v32i8 ||
1626 if (LocVT == MVT::v32i8 ||
1697 if (LocVT == MVT::v32i8 ||
[all …]
DX86GenFastISel.inc58 if (RetVT.SimpleTy != MVT::v32i8)
180 case MVT::v32i8: return fastEmit_ISD_ABS_MVT_v32i8_r(RetVT, Op0, Op0IsKill);
310 case MVT::v32i8: return fastEmit_ISD_ANY_EXTEND_MVT_v32i1_MVT_v32i8_r(Op0, Op0IsKill);
656 if (RetVT.SimpleTy != MVT::v32i8)
760 case MVT::v32i8: return fastEmit_ISD_CTPOP_MVT_v32i8_r(RetVT, Op0, Op0IsKill);
1435 case MVT::v32i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i1_MVT_v32i8_r(Op0, Op0IsKill);
1551 case MVT::v32i8: return fastEmit_ISD_SIGN_EXTEND_MVT_v32i8_r(RetVT, Op0, Op0IsKill);
2566 if (RetVT.SimpleTy != MVT::v32i8)
2879 case MVT::v32i8: return fastEmit_ISD_ZERO_EXTEND_MVT_v32i8_r(RetVT, Op0, Op0IsKill);
4849 case MVT::v32i8: return fastEmit_X86ISD_MOVMSK_MVT_v32i8_r(RetVT, Op0, Op0IsKill);
[all …]
DX86GenRegisterInfo.inc4492 /* 40 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPatternsHVX.td351 def: Pat<(VecI16 (sext_inreg HVI16:$Vs, v32i8)),
361 def: Pat<(VecI32 (sext_inreg HVI32:$Vs, v32i8)),
DHexagonISelLoweringHVX.cpp198 for (MVT T: {MVT::v32i8, MVT::v32i16, MVT::v16i8, MVT::v16i16, MVT::v16i32}) in initializeHVXLowering()
201 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32}) in initializeHVXLowering()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td52 def v32i8 : ValueType<256, 30>; // 32 x i8 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp175 case MVT::v32i8: return VectorType::get(Type::getInt8Ty(Context), 32); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td243 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp119 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Custom); in R600TargetLowering()
DSIISelLowering.cpp204 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand); in SITargetLowering()