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Searched refs:v4i32 (Results 1 – 25 of 169) sorted by relevance

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/third_party/ffmpeg/libavcodec/mips/
Dvp3dsp_idct_msa.c29 v4i32 r0_r, r0_l, r1_r, r1_l, r2_r, r2_l, r3_r, r3_l, in idct_msa()
31 v4i32 A, B, C, D, Ad, Bd, Cd, Dd, E, F, G, H; in idct_msa()
32 v4i32 Ed, Gd, Add, Bdd, Fd, Hd; in idct_msa()
35 v4i32 c0, c1, c2, c3, c4, c5, c6, c7; in idct_msa()
36 v4i32 f0, f1, f2, f3, f4, f5, f6, f7; in idct_msa()
37 v4i32 sign_t; in idct_msa()
40 v4i32 cnst64277w = {64277, 64277, 64277, 64277}; in idct_msa()
41 v4i32 cnst60547w = {60547, 60547, 60547, 60547}; in idct_msa()
42 v4i32 cnst54491w = {54491, 54491, 54491, 54491}; in idct_msa()
43 v4i32 cnst46341w = {46341, 46341, 46341, 46341}; in idct_msa()
[all …]
Dvc1dsp_msa.c31 v4i32 in_r0, in_r1, in_r2, in_r3, in_r4, in_r5, in_r6, in_r7; in ff_vc1_inv_trans_8x8_msa()
32 v4i32 in_l0, in_l1, in_l2, in_l3, in_l4, in_l5, in_l6, in_l7; in ff_vc1_inv_trans_8x8_msa()
33 v4i32 t_r1, t_r2, t_r3, t_r4, t_r5, t_r6, t_r7, t_r8; in ff_vc1_inv_trans_8x8_msa()
34 v4i32 t_l1, t_l2, t_l3, t_l4, t_l5, t_l6, t_l7, t_l8; in ff_vc1_inv_trans_8x8_msa()
35 v4i32 cnst_12 = {12, 12, 12, 12}; in ff_vc1_inv_trans_8x8_msa()
36 v4i32 cnst_4 = {4, 4, 4, 4}; in ff_vc1_inv_trans_8x8_msa()
37 v4i32 cnst_16 = {16, 16, 16, 16}; in ff_vc1_inv_trans_8x8_msa()
38 v4i32 cnst_6 = {6, 6, 6, 6}; in ff_vc1_inv_trans_8x8_msa()
39 v4i32 cnst_15 = {15, 15, 15, 15}; in ff_vc1_inv_trans_8x8_msa()
40 v4i32 cnst_9 = {9, 9, 9, 9}; in ff_vc1_inv_trans_8x8_msa()
[all …]
Dsimple_idct_msa.c31 v4i32 temp0_r, temp1_r, temp2_r, temp3_r; in simple_idct_msa()
32 v4i32 temp0_l, temp1_l, temp2_l, temp3_l; in simple_idct_msa()
33 v4i32 a0_r, a1_r, a2_r, a3_r, a0_l, a1_l, a2_l, a3_l; in simple_idct_msa()
34 v4i32 b0_r, b1_r, b2_r, b3_r, b0_l, b1_l, b2_l, b3_l; in simple_idct_msa()
35 v4i32 w2, w4, w6; in simple_idct_msa()
38 v4i32 const_val0 = __msa_ldi_w(1); in simple_idct_msa()
39 v4i32 const_val1 = __msa_ldi_w(1); in simple_idct_msa()
53 w2 = (v4i32) __msa_splati_h(weights, 2); in simple_idct_msa()
54 w2 = (v4i32) __msa_ilvr_h(zero, (v8i16) w2); in simple_idct_msa()
55 w4 = (v4i32) __msa_splati_h(weights, 4); in simple_idct_msa()
[all …]
Dvp9_intra_msa.c123 sum_w = (v4u32) __msa_srari_w((v4i32) sum_d, 3); in ff_dc_4x4_msa()
125 val0 = __msa_copy_u_w((v4i32) store, 0); in ff_dc_4x4_msa()
141 data = (v16i8) __msa_insert_w((v4i32) data, 0, val0); \
144 sum_w = (v4u32) __msa_srari_w((v4i32) sum_w, 2); \
146 val0 = __msa_copy_u_w((v4i32) store, 0); \
169 sum_w = (v4u32) __msa_pckev_w((v4i32) sum_d, (v4i32) sum_d); in ff_dc_8x8_msa()
171 sum_w = (v4u32) __msa_srari_w((v4i32) sum_d, 4); in ff_dc_8x8_msa()
197 sum_w = (v4u32) __msa_srari_w((v4i32) sum_d, 3); \
223 sum_w = (v4u32) __msa_pckev_w((v4i32) sum_d, (v4i32) sum_d); in ff_dc_16x16_msa()
225 sum_w = (v4u32) __msa_srari_w((v4i32) sum_d, 5); in ff_dc_16x16_msa()
[all …]
Dh264pred_msa.c144 v4i32 int_multiplier = { 0, 1, 2, 3 }; in intra_predict_plane_8x8_msa()
147 v4i32 vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7, vec8; in intra_predict_plane_8x8_msa()
158 res0 = __msa_copy_s_w((v4i32) sum, 0); in intra_predict_plane_8x8_msa()
212 v4i32 int_multiplier = { 0, 1, 2, 3 }; in intra_predict_plane_16x16_msa()
216 v4i32 vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7, vec8, res_add; in intra_predict_plane_16x16_msa()
217 v4i32 reg0, reg1, reg2, reg3; in intra_predict_plane_16x16_msa()
229 res_add = (v4i32) __msa_hadd_s_d(vec8, vec8); in intra_predict_plane_16x16_msa()
296 src0 = __msa_copy_u_w((v4i32) sum, 0); in intra_predict_dc_4blk_8x8_msa()
297 src1 = __msa_copy_u_w((v4i32) sum, 1); in intra_predict_dc_4blk_8x8_msa()
356 sum = (v4u32) __msa_srari_w((v4i32) sum, 2); in intra_predict_vert_dc_8x8_msa()
[all …]
Dvp8_idct_msa.c31 v4i32 a1_m, b1_m, c1_m, d1_m; \
32 v4i32 c_tmp1_m, c_tmp2_m, d_tmp1_m, d_tmp2_m; \
33 v4i32 const_cospi8sqrt2minus1_m, sinpi8_sqrt2_m; \
51 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ff_vp8_idct_add_msa()
52 v4i32 res0, res1, res2, res3; in ff_vp8_idct_add_msa()
108 v4i32 in0, in1, in2, in3, a1, b1, c1, d1; in ff_vp8_luma_dc_wht_msa()
109 v4i32 hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ff_vp8_luma_dc_wht_msa()
Dh264_deblock_msa.c52 ref_2 = (v16i8)__msa_ilvr_w((v4i32)ref_3, (v4i32)ref_2); \
53 ref_0 = (v16i8)__msa_ilvr_w((v4i32)ref_0, (v4i32)ref_0); \
54 ref_1 = (v16i8)__msa_ilvr_w((v4i32)ref_1, (v4i32)ref_1); \
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td412 [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
423 [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
426 [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
429 [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
450 [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
453 [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
456 [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
480 v4i32, v4i32, v16i8>;
481 def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
503 [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
[all …]
DPPCInstrVSX.td546 int_ppc_vsx_xvcmpeqsp, v4i32, v4f32>;
552 int_ppc_vsx_xvcmpgesp, v4i32, v4f32>;
558 int_ppc_vsx_xvcmpgtsp, v4i32, v4f32>;
678 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
686 [(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
698 [(set v4i32:$XT, (fp_to_sint v4f32:$XB))]>;
705 [(set v4i32:$XT, (fp_to_uint v4f32:$XB))]>;
717 [(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
721 [(set v4f32:$XT, (sint_to_fp v4i32:$XB))]>;
733 [(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
[all …]
/third_party/skia/third_party/externals/libwebp/src/dsp/
Dmsa_macro.h27 #define ADDVI_W(a, b) __msa_addvi_w((v4i32)a, b)
30 #define SRAI_W(a, b) __msa_srai_w((v4i32)a, b)
32 #define SLLI_B(a, b) __msa_slli_b((v4i32)a, b)
58 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
70 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
275 #define LD_SW2(...) LD_W2(v4i32, __VA_ARGS__)
282 #define LD_SW3(...) LD_W3(v4i32, __VA_ARGS__)
289 #define LD_SW4(...) LD_W4(v4i32, __VA_ARGS__)
329 #define ST_SW2(...) ST_W2(v4i32, __VA_ARGS__)
336 #define ST_SW3(...) ST_W3(v4i32, __VA_ARGS__)
[all …]
Dlossless_enc_msa.c23 v4i32 t4, t5; \
29 t4 = __msa_srli_w((v4i32)src0, 16); \
30 t5 = __msa_srli_w((v4i32)src1, 16); \
41 v4i32 t2; \
44 t2 = __msa_srli_w((v4i32)src, 16); \
83 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2); in TransformColor_MSA()
90 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 0); in TransformColor_MSA()
Denc_msa.c26 v4i32 a1_m, b1_m, c1_m, d1_m; \
27 const v4i32 cospi8sqrt2minus1 = __msa_fill_w(20091); \
28 const v4i32 sinpi8sqrt2 = __msa_fill_w(35468); \
29 v4i32 c_tmp1_m = in1 * sinpi8sqrt2; \
30 v4i32 c_tmp2_m = in3 * cospi8sqrt2minus1; \
31 v4i32 d_tmp1_m = in1 * cospi8sqrt2minus1; \
32 v4i32 d_tmp2_m = in3 * sinpi8sqrt2; \
47 v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3; in ITransformOne()
48 v4i32 res0, res1, res2, res3; in ITransformOne()
68 res0 = (v4i32)__msa_pckev_b((v16i8)vt0, (v16i8)vt1); in ITransformOne()
[all …]
Dlossless_msa.c40 pix_w = __msa_copy_s_w((v4i32)dst2, 0); \
58 uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2); \
84 v4i32 t4, t5; \
90 t4 = __msa_srli_w((v4i32)t0, 16); \
91 t5 = __msa_srli_w((v4i32)t1, 16); \
102 v4i32 t2; \
105 t2 = __msa_srli_w((v4i32)t0, 16); \
324 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 2); in TransformColorInverse_MSA()
331 const uint32_t pix_w = __msa_copy_s_w((v4i32)dst0, 0); in TransformColorInverse_MSA()
/third_party/ffmpeg/libavutil/mips/
Dgeneric_macros_msa.h37 #define LD_SW(...) LD_V(v4i32, __VA_ARGS__)
45 #define ST_SW(...) ST_V(v4i32, __VA_ARGS__)
281 #define LD_SW2(...) LD_V2(v4i32, __VA_ARGS__)
300 #define LD_SW4(...) LD_V4(v4i32, __VA_ARGS__)
339 #define LD_SW8(...) LD_V8(v4i32, __VA_ARGS__)
367 #define ST_SW2(...) ST_V2(v4i32, __VA_ARGS__)
377 #define ST_SW4(...) ST_V4(v4i32, __VA_ARGS__)
393 #define ST_SW8(...) ST_V8(v4i32, __VA_ARGS__)
447 out0_m = __msa_copy_u_w((v4i32) in, idx); \
453 out0_m = __msa_copy_u_w((v4i32) in, idx0); \
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc1241 /* 2631*/ OPC_SwitchType /*2 cases */, 19, MVT::v4i32,// ->2653
1246 MVT::v4i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
1247 …v4i32] } (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:…
1248 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2011 /* 4107*/ OPC_CheckType, MVT::v4i32,
2016 MVT::v4i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
2017 …v4i32] } (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:…
2018 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2038 /* 4159*/ OPC_CheckType, MVT::v4i32,
2043 MVT::v4i32, 5/*#Ops*/, 1, 0, 2, 3, 4,
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenDAGISel.inc79 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
83 …// Dst: (STXSIBXv (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$S, VSRC:{ *:[i32] }), xoaddr:{ …
96 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
100 …// Dst: (STXSIBXv (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v16i8] }:$S, VSRC:{ *:[i32] }), xoaddr:{ …
117 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
121 …// Dst: (STXSIHXv (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$S, VSRC:{ *:[i32] }), xoaddr:{ …
134 MVT::v4i32, 2/*#Ops*/, 1, 5, // Results = #6
138 …// Dst: (STXSIHXv (COPY_TO_REGCLASS:{ *:[v4i32] } ?:{ *:[v8i16] }:$S, VSRC:{ *:[i32] }), xoaddr:{ …
188 MVT::v4i32, 3/*#Ops*/, 1, 1, 5, // Results = #6
195 …// Dst: (DFSTOREf64 (EXTRACT_SUBREG:{ *:[f64] } (XXPERMDI:{ *:[v4i32] } ?:{ *:[v2i64] }:$A, ?:{ *:…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc482 /* 774*/ OPC_CheckChild1Type, MVT::v4i32,
491 …// Src: (st MSA128WOpnd:{ *:[v4i32] }:$wd, addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexe…
492 // Dst: (ST_W MSA128WOpnd:{ *:[v4i32] }:$wd, addrimm10lsl2:{ *:[iPTR] }:$addr)
1311 /* 2329*/ /*SwitchType*/ 14, MVT::v4i32,// ->2345
1316 MVT::v4i32, 2/*#Ops*/, 2, 3,
1317 …// Src: (ld:{ *:[v4i32] } addrimm10lsl2:{ *:[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predic…
1318 // Dst: (LD_W:{ *:[v4i32] } addrimm10lsl2:{ *:[iPTR] }:$addr)
8395 MVT::v4i32, 2/*#Ops*/, 0, 1,
8396 …// Src: (intrinsic_wo_chain:{ *:[v4i32] } 4178:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:…
8397 // Dst: (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
[all …]
/third_party/openh264/codec/common/inc/
Dmsa_macros.h295 out0_m = __msa_copy_u_w((v4i32) in, idx); \
301 out0_m = __msa_copy_u_w((v4i32) in, idx0); \
302 out1_m = __msa_copy_u_w((v4i32) in, idx1); \
309 out0_m = __msa_copy_u_w((v4i32) in, idx0); \
310 out1_m = __msa_copy_u_w((v4i32) in, idx1); \
311 out2_m = __msa_copy_u_w((v4i32) in, idx2); \
312 out3_m = __msa_copy_u_w((v4i32) in, idx3); \
428 out = (RTYPE) __msa_vshf_w((v4i32) mask, (v4i32) in0, (v4i32) in1); \
603 out = (RTYPE) __msa_ilvod_w((v4i32) in0, (v4i32) in1); \
703 out = (RTYPE) __msa_ilvl_w((v4i32) in0, (v4i32) in1); \
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
222 if (Args.size() == 2 && ISD == ISD::MUL && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
424 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence in getArithmeticInstrCost()
425 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
428 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence in getArithmeticInstrCost()
429 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
440 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()) in getArithmeticInstrCost()
442 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41()) in getArithmeticInstrCost()
467 { ISD::SHL, MVT::v4i32, 1 }, // pslld in getArithmeticInstrCost()
471 { ISD::SRL, MVT::v4i32, 1 }, // psrld. in getArithmeticInstrCost()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrSIMD.td25 defm "" : ARGUMENT<V128, v4i32>;
51 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
81 foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
120 defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>;
124 foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
149 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
197 defm "" : ConstVec<v4i32,
252 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
310 defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
323 def : ScalarSplatPat<v4i32, i32, I32>;
[all …]
/third_party/skia/third_party/externals/libpng/mips/
Dfilter_msa_intrinsics.c331 out0 = (RTYPE) __msa_ilvev_w((v4i32) in1, (v4i32) in0); \
332 out1 = (RTYPE) __msa_ilvev_w((v4i32) in3, (v4i32) in2); \
474 src0 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp0); in png_read_filter_row_sub4_msa()
515 src0 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp0); in png_read_filter_row_sub3_msa()
533 out1 = __msa_copy_s_w((v4i32) dst0, 2); in png_read_filter_row_sub3_msa()
558 src0 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp0); in png_read_filter_row_avg4_msa()
559 src1 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp1); in png_read_filter_row_avg4_msa()
562 out0 = __msa_copy_s_w((v4i32) src1, 0); in png_read_filter_row_avg4_msa()
613 src0 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp0); in png_read_filter_row_avg3_msa()
614 src1 = (v16u8) __msa_insert_w((v4i32) zero, 0, inp1); in png_read_filter_row_avg3_msa()
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DBUFInstructions.td221 (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i8:$format,
227 (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset,
268 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
274 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
505 …(load_vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$…
506 …(load_vt (inst v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$sw…
512 …(load_vt (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i…
513 …(load_vt (inst i64:$vaddr, v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe, i1:…
579 [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
584 [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset,
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp200 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
201 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
202 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
203 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
219 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
220 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
223 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
224 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
243 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
244 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
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DARMInstrMVE.td330 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "i", ?>;
331 def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "i", ?>;
338 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "s", 0b0>;
339 def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "s", 0b0>;
342 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "u", 0b1>;
343 def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "u", 0b1>;
353 def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b11, "p", 0b1>;
662 def : Pat<(i32 (vecreduce_add (v4i32 MQPR:$src))), (i32 (MVE_VADDVu32no_acc $src))>;
665 def : Pat<(i32 (add (i32 (vecreduce_add (v4i32 MQPR:$src1))), (i32 tGPR:$src2))),
798 def : Pat<(i32 (vecreduce_smax (v4i32 MQPR:$src))),
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DARMInstrNEON.td1078 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1099 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
1408 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
2143 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2193 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
3354 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3357 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3361 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3421 def v4i32 : N3VQ_cmp<op24, op23, 0b10, op11_8, op4, itinQ32,
3423 v4i32, v4i32, fc, Commutable>;
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