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Searched refs:v4i64 (Results 1 – 25 of 32) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp305 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
321 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
488 { ISD::MUL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
533 { ISD::SRA, MVT::v4i64, 1 }, in getArithmeticInstrCost()
567 { ISD::SHL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
568 { ISD::SRL, MVT::v4i64, 1 }, in getArithmeticInstrCost()
610 { ISD::SHL, MVT::v4i64, 2+2 }, in getArithmeticInstrCost()
611 { ISD::SRL, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
612 { ISD::SRA, MVT::v4i64, 4+2 }, in getArithmeticInstrCost()
633 { ISD::SHL, MVT::v4i64, 2+2 }, // 2*psllq + split. in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td73 defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>;
95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
117 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>;
126 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32, sub_xmm>;
140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
DX86CallingConv.td115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
743 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td160 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
558 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
566 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
2130 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2132 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2134 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2136 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2177 def : Pat<(X86movmsk (v4i64 VR256:$src)),
2244 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2246 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
[all …]
DX86InstrFragmentsSIMD.td802 def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
849 // NOTE: all 256-bit integer vector loads are promoted to v4i64
855 (v4i64 (alignedload node:$ptr))>;
933 return Mgt->getIndex().getValueType() == MVT::v4i64;
961 return Sc->getIndex().getValueType() == MVT::v4i64;
993 def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
DX86InstrAVX512.td456 def : Pat<(v4i64 immAllZerosV), (AVX512_256_SET0)>;
922 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
951 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)),
1409 def : Pat<(v4i64 (X86VBroadcast (v2i64 (X86vzload64 addr:$src)))),
1496 def : Pat<(v8i64 (X86SubVBroadcast (v4i64 VR256X:$src))),
1498 (v4i64 VR256X:$src), 1)>;
1564 def : Pat<(v4i64 (X86SubVBroadcast (loadv2i64 addr:$src))),
1581 (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))),
1585 (bc_v8i32 (v4i64 (X86SubVBroadcast (loadv2i64 addr:$src)))),
1598 def : Pat<(v4i64 (X86SubVBroadcast (v2i64 VR128X:$src))),
[all …]
DX86ISelLowering.cpp1021 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1123 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1124 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1127 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1128 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i64, Custom); in X86TargetLowering()
1134 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1142 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1157 addRegisterClass(MVT::v4i64, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1208 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) { in X86TargetLowering()
1228 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); in X86TargetLowering()
[all …]
DX86RegisterInfo.td559 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
592 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86ISelDAGToDAG.cpp4035 case MVT::v4i64: in getVPTESTMOpc()
4057 case MVT::v4i64: in getVPTESTMOpc()
4082 case MVT::v4i64: in getVPTESTMOpc()
4112 case MVT::v4i64: in getVPTESTMOpc()
4134 case MVT::v4i64: in getVPTESTMOpc()
4159 case MVT::v4i64: in getVPTESTMOpc()
DX86InstrXOP.td370 defm VPCMOVY : xop4op_int<0xA2, "vpcmov", VR256, i256mem, v4i64,
DX86FastISel.cpp427 case MVT::v4i64: in X86FastEmitLoad()
600 case MVT::v4i64: in X86FastEmitStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h109 v4i64 = 59, // 4 x i64 enumerator
362 SimpleTy == MVT::v4i64 || SimpleTy == MVT::v256i1); in is256BitVector()
497 case v4i64: in getVectorElementType()
620 case v4i64: in getVectorNumElements()
780 case v4i64: in getSizeInBits()
976 if (NumElements == 4) return MVT::v4i64; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1322 …dd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPADDQYrr:{ *:[v4i64]…
1333 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPADDQZ256rr:{ *:[v4i6…
1910 …ub:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPSUBQYrr:{ *:[v4i64]…
1921 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPSUBQZ256rr:{ *:[v4i6…
2390 … *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPMULLQZ256rr:{ *:[v4i6…
3622 …and:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPANDYrr:{ *:[v4i64]…
3633 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPANDQZ256rr:{ *:[v4i6…
3644 …nd:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VANDPSYrr:{ *:[v4i64]…
5196 …(or:{ *:[v4i64] } VR256:{ *:[v4i64] }:$src1, VR256:{ *:[v4i64] }:$src2) => (VPORYrr:{ *:[v4i64] …
5207 …{ *:[v4i64] } VR256X:{ *:[v4i64] }:$src1, VR256X:{ *:[v4i64] }:$src2) => (VPORQZ256rr:{ *:[v4i64…
[all …]
DX86GenCallingConv.inc243 LocVT == MVT::v4i64) {
916 LocVT == MVT::v4i64 ||
1009 LocVT == MVT::v4i64 ||
1138 LocVT == MVT::v4i64 ||
1186 LocVT == MVT::v4i64 ||
1250 LocVT == MVT::v4i64 ||
1563 LocVT == MVT::v4i64 ||
1629 LocVT == MVT::v4i64 ||
1700 LocVT == MVT::v4i64 ||
1988 LocVT == MVT::v4i64 ||
[all …]
DX86GenFastISel.inc160 if (RetVT.SimpleTy != MVT::v4i64)
189 case MVT::v4i64: return fastEmit_ISD_ABS_MVT_v4i64_r(RetVT, Op0, Op0IsKill);
229 case MVT::v4i64: return fastEmit_ISD_ANY_EXTEND_MVT_v4i1_MVT_v4i64_r(Op0, Op0IsKill);
585 if (RetVT.SimpleTy != MVT::v4i64)
611 case MVT::v4i64: return fastEmit_ISD_CTLZ_MVT_v4i64_r(RetVT, Op0, Op0IsKill);
737 if (RetVT.SimpleTy != MVT::v4i64)
769 case MVT::v4i64: return fastEmit_ISD_CTPOP_MVT_v4i64_r(RetVT, Op0, Op0IsKill);
1354 case MVT::v4i64: return fastEmit_ISD_SIGN_EXTEND_MVT_v4i1_MVT_v4i64_r(Op0, Op0IsKill);
1519 if (RetVT.SimpleTy != MVT::v4i64)
1634 …case MVT::v4i64: return fastEmit_ISD_SIGN_EXTEND_VECTOR_INREG_MVT_v16i8_MVT_v4i64_r(Op0, Op0IsKill…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
612 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4 * AmortizationCost }, in getCmpSelInstrCost()
DAArch64SelectionDAGInfo.cpp89 MVT::v4i64, in EmitUnrolledSetTag()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp223 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
227 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
228 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
454 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 }, in getCmpSelInstrCost()
DARMRegisterInfo.td524 def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
538 def DQuad : RegisterClass<"ARM", [v4i64], 256,
579 def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
DARMISelDAGToDAG.cpp2216 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVST()
2222 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0); in SelectVST()
2384 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0); in SelectVLDSTLane()
2391 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td84 def v4i64 : ValueType<256, 59>; // 4 x i64 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp204 case MVT::v4i64: return VectorType::get(Type::getInt64Ty(Context), 4); in getTypeForEVT()
/third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/ray_tracing/
DvktRayTracingDataSpillTests.cpp1387 using v4i64 = tcu::Vector<deInt64, 4>; typedef
1543 else if (dataType == DataType::INT64) GEN_V4_FILL(v4i64); in fillInputBuffer()
/third_party/vk-gl-cts/external/vulkancts/modules/vulkan/ray_tracing/
DvktRayTracingDataSpillTests.cpp1387 using v4i64 = tcu::Vector<deInt64, 4>; typedef
1543 else if (dataType == DataType::INT64) GEN_V4_FILL(v4i64); in fillInputBuffer()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td267 def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64

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