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Searched refs:v8f16 (Results 1 – 25 of 38) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
D	ARMInstrMVE.td	347 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, 0b01, "f", ?>; 1093 def : Pat<(v8f16 (fmaxnum (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))), 1094 (v8f16 (MVE_VMAXNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>; 1100 def : Pat<(v8f16 (int_arm_mve_max_predicated (v8f16 MQPR:$val1), (v8f16 MQPR:$val2), (i32 0), 1101 (v8i1 VCCR:$mask), (v8f16 MQPR:$inactive))), 1102 (v8f16 (MVE_VMAXNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2), 1104 (v8f16 MQPR:$inactive)))>; 1113 def : Pat<(v8f16 (fminnum (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))), 1114 (v8f16 (MVE_VMINNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>; 1120 def : Pat<(v8f16 (int_arm_mve_min_predicated (v8f16 MQPR:$val1), (v8f16 MQPR:$val2), [all …]
D	ARMCallingConv.td	34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 186 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 212 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 234 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
D	ARMInstrNEON.td	1084 def : Pat<(vector_insert (v8f16 QPR:$src), 1105 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; 2153 def : Pat<(store (extractelt (v8f16 QPR:$src), imm:$lane), addrmode6:$addr), 3364 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4, 3367 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>, 4263 v8f16, v8f16, fadd, 1>, 4326 v8f16, v8f16, fmul, 1>, 4334 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16, 4357 def : Pat<(v8f16 (fmul (v8f16 QPR:$src1), 4358 (v8f16 (ARMvduplane (v8f16 QPR:$src2), imm:$lane)))), [all …]
D	ARMCallingConv.cpp	`221 case MVT::v8f16: in CC_ARM_AAPCS_Custom_Aggregate()`
D	ARMISelDAGToDAG.cpp	`1753 LoadedVT == MVT::v8f16) && in tryMVEIndexedLoad() 2039 case MVT::v8f16: in SelectVLD() 2181 case MVT::v8f16: in SelectVST() 2346 case MVT::v8f16: in SelectVLDSTLane() 2727 case MVT::v8f16: in SelectVLDDup() 3671 case MVT::v8f16: in Select() 3694 case MVT::v8f16: in Select() 3716 case MVT::v8f16: in Select()`
D	ARMRegisterInfo.td	`438 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128, 463 def MQPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16],`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
D	ARMGenDAGISel.inc	10704 /* 22627/ OPC_CheckChild0Type, MVT::v8f16, 10723 …1] } VCCR:{ :[v8i1] }:$p1, (ARMvcmp:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (ARMvdup:{ :[v8f16] } H… 10724 …// Dst: (MVE_VCMPf16r:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } HPR:{ :[… 10738 …1] } VCCR:{ :[v8i1] }:$p1, (ARMvcmp:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (ARMvdup:{ :[v8f16] } H… 10739 …// Dst: (MVE_VCMPf16r:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } HPR:{ :[… 10753 …1] } VCCR:{ :[v8i1] }:$p1, (ARMvcmp:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (ARMvdup:{ :[v8f16] } H… 10754 …// Dst: (MVE_VCMPf16r:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } HPR:{ :[… 10768 …1] } VCCR:{ :[v8i1] }:$p1, (ARMvcmp:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (ARMvdup:{ :[v8f16] } H… 10769 …// Dst: (MVE_VCMPf16r:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (COPY_TO_REGCLASS:{ :[i32] } HPR:{ :[… 10783 …1] } VCCR:{ :[v8i1] }:$p1, (ARMvcmp:{ :[v8i1] } MQPR:{ :[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H… [all …]
D	ARMGenCallingConv.inc	`76 LocVT == MVT::v8f16 \|\| 246 LocVT == MVT::v8f16 \|\| 365 LocVT == MVT::v8f16 \|\| 432 LocVT == MVT::v8f16 \|\| 526 LocVT == MVT::v8f16 \|\| 614 LocVT == MVT::v8f16 \|\| 717 LocVT == MVT::v8f16 \|\| 831 LocVT == MVT::v8f16 \|\| 888 LocVT == MVT::v8f16 \|\|`
D	ARMGenGlobalISel.inc	7976 …// (concat_vectors:{ :[v8f16] } DPR:{ :[v4f16] }:$Dn, DPR:{ :[v4f16] }:$Dm) => (REG_SEQUENCE:… 8785 // (bitconvert:{ :[v2f64] } QPR:{ :[v8f16] }:$src) => QPR:{ :[v2f64] }:$src 8855 // (bitconvert:{ :[v2i64] } QPR:{ :[v8f16] }:$src) => QPR:{ :[v2i64] }:$src 8929 …// (bitconvert:{ :[v2f64] } QPR:{ :[v8f16] }:$src) => (VREV64q16:{ :[v2f64] } QPR:{ :[v8f16]… 9009 …// (bitconvert:{ :[v2i64] } QPR:{ :[v8f16] }:$src) => (VREV64q16:{ :[v2i64] } QPR:{ :[v8f16]… 9113 // (bitconvert:{ :[v2f64] } MQPR:{ :[v8f16] }:$src) => MQPR:{ :[v2f64] }:$src 9183 // (bitconvert:{ :[v2i64] } MQPR:{ :[v8f16] }:$src) => MQPR:{ :[v2i64] }:$src 9265 …// (bitconvert:{ :[v2f64] } MQPR:{ :[v8f16] }:$src) => (MVE_VREV64_16:{ :[v2f64] } MQPR:{ :[… 9365 …// (bitconvert:{ :[v2i64] } MQPR:{ :[v8f16] }:$src) => (MVE_VREV64_16:{ :[v2i64] } MQPR:{ :[… 9813 // (bitconvert:{ :[v4f32] } QPR:{ :[v8f16] }:$src) => QPR:{ :[v4f32] }:$src [all …]
D	ARMGenFastISel.inc	503 if (RetVT.SimpleTy != MVT::v8f16) 521 case MVT::v8f16: return fastEmit_ARMISD_VREV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 601 if (RetVT.SimpleTy != MVT::v8f16) 642 case MVT::v8f16: return fastEmit_ARMISD_VREV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 964 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill); 1179 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0, Op0IsKill); 1286 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0, Op0IsKill); 1500 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0, Op0IsKill); 1561 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill); 1581 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill); [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64ISelDAGToDAG.cpp	3191 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3218 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3245 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3272 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3299 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3326 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3353 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3380 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3407 } else if (VT == MVT::v8i16 \|\| VT == MVT::v8f16) { in Select() 3429 VT == MVT::v8f16) { in Select() [all …]
D	AArch64CallingConvention.td	38 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 112 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 120 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 137 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 154 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 229 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 244 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 265 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 287 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
D	AArch64InstrInfo.td	805 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))), 806 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>; 807 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))), 808 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>; 2096 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>; 2152 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>; 2305 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 2488 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 2815 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>; 2838 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>; [all …]
D	AArch64InstrFormats.td	5259 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128, 5261 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; 5281 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128, 5283 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; 5303 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128, 5305 [(set (v8f16 V128:$dst), 5306 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>; 5444 def v8f16 : BaseSIMDThreeSameVectorFML<1, U, b13, size, asm, ".4s", ".4h", V128, 5445 v4f32, v8f16, OpNode>; 5700 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128, [all …]
D	AArch64ISelLowering.cpp	163 addQRTypeForNEON(MVT::v8f16); in AArch64TargetLowering() 401 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering() 404 setOperationAction(ISD::FPOW, MVT::v8f16, Expand); in AArch64TargetLowering() 407 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand); in AArch64TargetLowering() 410 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering() 413 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering() 416 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering() 419 setOperationAction(ISD::FEXP, MVT::v8f16, Expand); in AArch64TargetLowering() 422 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); in AArch64TargetLowering() 425 setOperationAction(ISD::FLOG, MVT::v8f16, Expand); in AArch64TargetLowering() [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
D	MachineValueType.h	`122 v8f16 = 67, // 8 x f16 enumerator 353 SimpleTy == MVT::v8f16 \|\| SimpleTy == MVT::v4f32 \|\| in is128BitVector() 511 case v8f16: in getVectorElementType() 603 case v8f16: in getVectorNumElements() 764 case v8f16: in getSizeInBits() 988 if (NumElements == 8) return MVT::v8f16; in getVectorVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
D	AArch64GenCallingConv.inc	`78 LocVT == MVT::v8f16 \|\| 331 LocVT == MVT::v8f16) { 378 LocVT == MVT::v8f16) { 574 LocVT == MVT::v8f16) { 638 LocVT == MVT::v8f16) { 722 LocVT == MVT::v8f16) { 804 LocVT == MVT::v8f16) { 1034 LocVT == MVT::v8f16 \|\| 1144 LocVT == MVT::v8f16) {`
D	AArch64GenFastISel.inc	743 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 811 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 879 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 947 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1015 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1443 if (RetVT.SimpleTy != MVT::v8f16) 1455 case MVT::v8f16: return fastEmit_AArch64ISD_REV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 1523 if (RetVT.SimpleTy != MVT::v8f16) 1549 case MVT::v8f16: return fastEmit_AArch64ISD_REV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill); 2039 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill); [all …]
D	AArch64GenGlobalISel.inc	8503 …// (concat_vectors:{ :[v8f16] } V64:{ :[v4f16] }:$Rd, V64:{ :[v4f16] }:$Rn) => (INSvi64lane:{… 9952 // (bitconvert:{ :[f128] } FPR128:{ :[v8f16] }:$src) => FPR128:{ :[f128] }:$src 10048 …8:{ :[v8f16] }:$src) => (EXTv16i8:{ :[f128] } (REV64v8i16:{ :[f128] } FPR128:{ :[v8f16] }:$s… 10574 // (bitconvert:{ :[v2f64] } FPR128:{ :[v8f16] }:$src) => FPR128:{ :[v2f64] }:$src 10654 …// (bitconvert:{ :[v2f64] } FPR128:{ :[v8f16] }:$src) => (REV64v8i16:{ :[v2f64] } FPR128:{ :… 10770 // (bitconvert:{ :[v2i64] } FPR128:{ :[v8f16] }:$src) => FPR128:{ :[v2i64] }:$src 10844 …// (bitconvert:{ :[v2i64] } FPR128:{ :[v8f16] }:$src) => (REV64v8i16:{ :[v2i64] } FPR128:{ :… 11454 // (bitconvert:{ :[v4f32] } FPR128:{ :[v8f16] }:$src) => FPR128:{ :[v4f32] }:$src 11547 …// (bitconvert:{ :[v4f32] } FPR128:{ :[v8f16] }:$src) => (REV32v8i16:{ :[v4f32] } FPR128:{ :… 11674 // (bitconvert:{ :[v4i32] } FPR128:{ :[v8f16] }:$src) => FPR128:{ :[v4i32] }:$src [all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
D	MipsMSAInstrInfo.td	3566 def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3570 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3598 def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3601 def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3609 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3622 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3628 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3634 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3640 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3697 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; [all …]
D	MipsSEInstrInfo.cpp	`275 TRI->isTypeLegalForClass(RC, MVT::v8f16)) in storeRegToStack() 353 TRI->isTypeLegalForClass(RC, MVT::v8f16)) in loadRegFromStack()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
D	ValueTypes.td	`94 def v8f16 : ValueType<128, 67>; // 8 x f16 vector value`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
D	ValueTypes.cpp	`212 case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8); in getTypeForEVT()`
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
D	MipsGenDAGISel.inc	506 /* 818/ OPC_CheckChild1Type, MVT::v8f16, 515 …// Src: (st MSA128H:{ :[v8f16] }:$ws, addrimm10lsl1:{ :[iPTR] }:$addr)<<P:Predicate_unindexedsto… 516 // Dst: (ST_H MSA128H:{ :[v8f16] }:$ws, addrimm10lsl1:{ :[iPTR] }:$addr) 1349 / 2415/ /SwitchType/ 14, MVT::v8f16,// ->2431 1354 MVT::v8f16, 2/#Ops/, 2, 3, 1355 …// Src: (ld:{ :[v8f16] } addrimm10lsl1:{ :[iPTR] }:$addr)<<P:Predicate_unindexedload>><<P:Predic… 1356 // Dst: (LD_H:{ :[v8f16] } addrimm10lsl1:{ :[iPTR] }:$addr) 10528 MVT::v8f16, 2/#Ops/, 0, 1, 10529 …// Src: (intrinsic_wo_chain:{ :[v8f16] } 3902:{ :[iPTR] }, MSA128WOpnd:{ :[v4f32] }:$ws, MSA128… 10530 … // Dst: (FEXDO_H:{ :[v8f16] } MSA128WOpnd:{ :[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt) [all …]
D	MipsGenGlobalISel.inc	3313 …// (bitconvert:{ :[v2i64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } v8f16:… 3363 …// (bitconvert:{ :[v2f64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } v8f16:… 3501 …[v2i64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2i64] } (SHF_H:{ :[v8i16] } (COP… 3525 …[v2f64] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v2f64] } (SHF_H:{ :[v8i16] } (COP… 3722 …// (bitconvert:{ :[v4i32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } v8f16:… 3772 …// (bitconvert:{ :[v4f32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } v8f16:… 3888 …[v4i32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4i32] } (SHF_H:{ :[v8i16] } (COP… 3912 …[v4f32] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v4f32] } (SHF_H:{ :[v8i16] } (COP… 4034 …// (bitconvert:{ :[v8i16] } v8f16:{ :[v8f16] }:$src) => (COPY_TO_REGCLASS:{ :[v8i16] } v8f16:… 4044 …// (bitconvert:{ :[v8f16] } v8i16:{ :[v8i16] }:$src) => (COPY_TO_REGCLASS:{ :[v8f16] } v8i16:… [all …]