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Searched refs:v8f32 (Results 1 – 25 of 29) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp696 { ISD::FADD, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
698 { ISD::FSUB, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
700 { ISD::FMUL, MVT::v8f32, 1 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
704 { ISD::FDIV, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/ in getArithmeticInstrCost()
741 { ISD::FDIV, MVT::v8f32, 28 }, // SNB from http://www.agner.org/ in getArithmeticInstrCost()
1047 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps in getShuffleCost()
1062 {TTI::SK_PermuteTwoSrc, MVT::v8f32, 1}, // vpermt2ps in getShuffleCost()
1077 {TTI::SK_Broadcast, MVT::v8f32, 1}, // vbroadcastps in getShuffleCost()
1084 {TTI::SK_Reverse, MVT::v8f32, 1}, // vpermps in getShuffleCost()
1094 {TTI::SK_PermuteSingleSrc, MVT::v8f32, 1}, // vpermps in getShuffleCost()
[all …]
DX86InstrFMA.td126 loadv4f32, loadv8f32, X86any_Fmadd, v4f32, v8f32,
129 loadv4f32, loadv8f32, X86Fmsub, v4f32, v8f32,
132 loadv4f32, loadv8f32, X86Fmaddsub, v4f32, v8f32,
135 loadv4f32, loadv8f32, X86Fmsubadd, v4f32, v8f32,
157 loadv8f32, X86Fnmadd, v4f32, v8f32, SchedWriteFMA>;
159 loadv8f32, X86Fnmsub, v4f32, v8f32, SchedWriteFMA>;
558 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86any_Fmadd, v4f32, v8f32,
560 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32,
562 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32,
564 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32,
[all …]
DX86InstrVecCompiler.td72 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
94 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
155 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32, sub_ymm>;
DX86CallingConv.td115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
743 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrSSE.td161 def : Pat<(v8f32 immAllZerosV), (AVX_SET0)>;
289 def : Pat<(v8f32 (X86vzload32 addr:$src)),
304 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
307 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)))), sub_xmm)>;
418 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>,
426 [(store (v8f32 VR256:$src), addr:$dst)]>,
1158 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, load,
1458 (v8i32 (X86cvtp2Int (v8f32 VR256:$src))))]>,
1541 (v8i32 (X86any_cvttp2si (v8f32 VR256:$src))))]>,
1937 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, v8f32,
[all …]
DX86ISelLowering.cpp755 for (auto VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, in X86TargetLowering()
1155 addRegisterClass(MVT::v8f32, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1162 for (auto VT : { MVT::v8f32, MVT::v4f64 }) { in X86TargetLowering()
1191 setOperationAction(ISD::STRICT_FADD, MVT::v8f32, Legal); in X86TargetLowering()
1193 setOperationAction(ISD::STRICT_FSUB, MVT::v8f32, Legal); in X86TargetLowering()
1195 setOperationAction(ISD::STRICT_FMUL, MVT::v8f32, Legal); in X86TargetLowering()
1197 setOperationAction(ISD::STRICT_FDIV, MVT::v8f32, Legal); in X86TargetLowering()
1200 setOperationAction(ISD::STRICT_FSQRT, MVT::v8f32, Legal); in X86TargetLowering()
1232 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); in X86TargetLowering()
1259 for (auto VT : { MVT::f32, MVT::f64, MVT::v4f32, MVT::v8f32, in X86TargetLowering()
[all …]
DX86InstrFragmentsSIMD.td800 def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
851 (v8f32 (alignedload node:$ptr))>;
994 def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
DX86RegisterInfo.td559 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
592 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86InstrXOP.td470 v8f32, loadv8f32, loadv8i32,
DX86InstrAVX512.td457 def : Pat<(v8f32 immAllZerosV), (AVX512_256_SET0)>;
934 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
963 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm)),
1493 def : Pat<(v16f32 (X86SubVBroadcast (v8f32 VR256X:$src))),
1495 (v8f32 VR256X:$src), 1)>;
1574 (v8f32 immAllZerosV)),
1595 def : Pat<(v8f32 (X86SubVBroadcast (v4f32 VR128X:$src))),
1596 (VINSERTF32x4Z256rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
1622 (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
1626 (bc_v4f64 (v8f32 (X86SubVBroadcast (loadv4f32 addr:$src)))),
[all …]
DX86FastISel.cpp404 case MVT::v8f32: in X86FastEmitLoad()
579 case MVT::v8f32: in X86FastEmitStore()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h130 v8f32 = 75, // 8 x f32 enumerator
359 return (SimpleTy == MVT::v16f16 || SimpleTy == MVT::v8f32 || in is256BitVector()
522 case v8f32: in getVectorElementType()
604 case v8f32: in getVectorNumElements()
782 case v8f32: in getSizeInBits()
998 if (NumElements == 8) return MVT::v8f32; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp258 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
259 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
260 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
261 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
287 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
288 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp348 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost()
349 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
350 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 10 }, in getCastInstrCost()
351 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc240 if (LocVT == MVT::v8f32 ||
917 LocVT == MVT::v8f32 ||
1010 LocVT == MVT::v8f32 ||
1139 LocVT == MVT::v8f32 ||
1187 LocVT == MVT::v8f32 ||
1251 LocVT == MVT::v8f32 ||
1564 LocVT == MVT::v8f32 ||
1630 LocVT == MVT::v8f32 ||
1701 LocVT == MVT::v8f32 ||
1989 LocVT == MVT::v8f32 ||
[all …]
DX86GenFastISel.inc948 case MVT::v8f32: return fastEmit_ISD_FP_EXTEND_MVT_v8f32_r(RetVT, Op0, Op0IsKill);
1161 if (RetVT.SimpleTy != MVT::v8f32)
1223 case MVT::v8f32: return fastEmit_ISD_FSQRT_MVT_v8f32_r(RetVT, Op0, Op0IsKill);
1805 case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0, Op0IsKill);
1867 case MVT::v8f32: return fastEmit_ISD_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0, Op0IsKill);
1923 case MVT::v8f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_v8f32_r(RetVT, Op0, Op0IsKill);
2136 if (RetVT.SimpleTy != MVT::v8f32)
2198 case MVT::v8f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v8f32_r(RetVT, Op0, Op0IsKill);
2303 case MVT::v8f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i32_MVT_v8f32_r(Op0, Op0IsKill);
2365 case MVT::v8f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v8i64_MVT_v8f32_r(Op0, Op0IsKill);
[all …]
DX86GenGlobalISel.inc7571 … (intrinsic_wo_chain:{ *:[v8f32] } 7437:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src) => (VFRCZPSYrr:{…
8965 …v8f32] } 6373:{ *:[iPTR] }, VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2, (timm:{ *:[i8] }…
13018 …dd:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VADDPSYrr:{ *:[v8f32]…
13030 …{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VADDPSZ256rr:{ *:[v8f3…
13339 …ub:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VSUBPSYrr:{ *:[v8f32]…
13351 …{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VSUBPSZ256rr:{ *:[v8f3…
13660 …ul:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VMULPSYrr:{ *:[v8f32]…
13672 …{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VMULPSZ256rr:{ *:[v8f3…
13981 …iv:{ *:[v8f32] } VR256:{ *:[v8f32] }:$src1, VR256:{ *:[v8f32] }:$src2) => (VDIVPSYrr:{ *:[v8f32]…
13993 …{ *:[v8f32] } VR256X:{ *:[v8f32] }:$src1, VR256X:{ *:[v8f32] }:$src2) => (VDIVPSZ256rr:{ *:[v8f3…
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td549 def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {
553 def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {
557 def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
633 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
DSIInstructions.td905 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
908 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index)
1048 def : BitConvert <v8i32, v8f32, SReg_256>;
1049 def : BitConvert <v8f32, v8i32, SReg_256>;
1050 def : BitConvert <v8i32, v8f32, VReg_256>;
1051 def : BitConvert <v8f32, v8i32, VReg_256>;
1422 defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">;
DAMDGPUCallingConv.td125 CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
DAMDGPUISelLowering.cpp85 setOperationAction(ISD::LOAD, MVT::v8f32, Promote); in AMDGPUTargetLowering()
86 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
156 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
163 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
185 setOperationAction(ISD::STORE, MVT::v8f32, Promote); in AMDGPUTargetLowering()
186 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32); in AMDGPUTargetLowering()
220 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand); in AMDGPUTargetLowering()
233 setTruncStoreAction(MVT::v8f64, MVT::v8f32, Expand); in AMDGPUTargetLowering()
285 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
294 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
DSMInstructions.td820 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX8", v8f32>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td102 def v8f32 : ValueType<256, 75>; // 8 x f32 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp220 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8); in getTypeForEVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp3627 Info.memVT = MVT::v8f32; in getTgtMemIntrinsic()
3707 Info.memVT = MVT::v8f32; in getTgtMemIntrinsic()

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