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Searched refs:v8i32 (Results 1 – 25 of 36) sorted by relevance

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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp392 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
394 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
395 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
422 { ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
423 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
426 { ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split. in getArithmeticInstrCost()
427 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
436 if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
438 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX()) in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td71 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
115 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>;
116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
117 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>;
118 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>;
119 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>;
120 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>;
124 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>;
125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
[all …]
DX86InstrSSE.td154 [(set VR256:$dst, (v8i32 immAllZerosV))]>;
173 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
177 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
308 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
311 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)))), sub_xmm)>;
560 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
568 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1158 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, i256mem, v8f32, v8i32, load,
1458 (v8i32 (X86cvtp2Int (v8f32 VR256:$src))))]>,
1463 (v8i32 (X86cvtp2Int (loadv8f32 addr:$src))))]>,
[all …]
DX86CallingConv.td115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
551 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
573 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
621 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
685 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
743 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
[all …]
DX86InstrFragmentsSIMD.td803 def loadv8i32 : PatFrag<(ops node:$ptr), (v8i32 (load node:$ptr))>;
857 (v8i32 (alignedload node:$ptr))>;
922 return Mgt->getIndex().getValueType() == MVT::v8i32;
967 return Sc->getIndex().getValueType() == MVT::v8i32;
992 def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
DX86ISelLowering.cpp1134 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1142 MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) in X86TargetLowering()
1153 addRegisterClass(MVT::v8i32, Subtarget.hasVLX() ? &X86::VR256XRegClass in X86TargetLowering()
1180 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1181 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1182 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1183 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i16, MVT::v8i32); in X86TargetLowering()
1184 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in X86TargetLowering()
1185 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v8i32, Legal); in X86TargetLowering()
1187 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); in X86TargetLowering()
[all …]
DX86InstrAVX512.td43 // v # NumElts # EltVT, so for vector of 8 elements of i32 it will be v8i32
445 [(set VR256X:$dst, (v8i32 immAllZerosV))]>;
930 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
959 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm)),
1415 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
1499 def : Pat<(v16i32 (X86SubVBroadcast (v8i32 VR256X:$src))),
1501 (v8i32 VR256X:$src), 1)>;
1582 (v8i32 immAllZerosV)),
1601 def : Pat<(v8i32 (X86SubVBroadcast (v4i32 VR128X:$src))),
1602 (VINSERTI32x4Z256rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
[all …]
DX86RegisterInfo.td559 def VR256 : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
592 def VR256X : RegisterClass<"X86", [v8f32, v4f64, v32i8, v16i16, v8i32, v4i64],
DX86ISelDAGToDAG.cpp4033 case MVT::v8i32: in getVPTESTMOpc()
4055 case MVT::v8i32: in getVPTESTMOpc()
4080 case MVT::v8i32: in getVPTESTMOpc()
4110 case MVT::v8i32: in getVPTESTMOpc()
4132 case MVT::v8i32: in getVPTESTMOpc()
4157 case MVT::v8i32: in getVPTESTMOpc()
DX86InstrXOP.td401 def : Pat<(v8i32 (or (and VR256:$src3, VR256:$src1),
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h97 v8i32 = 48, // 8 x i32 enumerator
361 SimpleTy == MVT::v16i16 || SimpleTy == MVT::v8i32 || in is256BitVector()
480 case v8i32: in getVectorElementType()
601 case v8i32: in getVectorNumElements()
779 case v8i32: in getSizeInBits()
963 if (NumElements == 8) return MVT::v8i32; in getVectorVT()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1435 …dd:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPADDDYrr:{ *:[v8i32]…
1446 …{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPADDDZ256rr:{ *:[v8i3…
1979 …ub:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPSUBDYrr:{ *:[v8i32]…
1990 …{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPSUBDZ256rr:{ *:[v8i3…
2446 …ul:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPMULLDYrr:{ *:[v8i32…
2457 … *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPMULLDZ256rr:{ *:[v8i3…
3747 …{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPANDDZ256rr:{ *:[v8i3…
3758 …and:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VPANDYrr:{ *:[v8i32]…
3769 …nd:{ *:[v8i32] } VR256:{ *:[v8i32] }:$src1, VR256:{ *:[v8i32] }:$src2) => (VANDPSYrr:{ *:[v8i32]…
5321 …{ *:[v8i32] } VR256X:{ *:[v8i32] }:$src1, VR256X:{ *:[v8i32] }:$src2) => (VPORDZ256rr:{ *:[v8i32…
[all …]
DX86GenFastISel.inc130 if (RetVT.SimpleTy != MVT::v8i32)
186 case MVT::v8i32: return fastEmit_ISD_ABS_MVT_v8i32_r(RetVT, Op0, Op0IsKill);
258 case MVT::v8i32: return fastEmit_ISD_ANY_EXTEND_MVT_v8i1_MVT_v8i32_r(Op0, Op0IsKill);
558 if (RetVT.SimpleTy != MVT::v8i32)
608 case MVT::v8i32: return fastEmit_ISD_CTLZ_MVT_v8i32_r(RetVT, Op0, Op0IsKill);
710 if (RetVT.SimpleTy != MVT::v8i32)
766 case MVT::v8i32: return fastEmit_ISD_CTPOP_MVT_v8i32_r(RetVT, Op0, Op0IsKill);
1383 case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i1_MVT_v8i32_r(Op0, Op0IsKill);
1503 case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i16_MVT_v8i32_r(Op0, Op0IsKill);
1555 case MVT::v8i32: return fastEmit_ISD_SIGN_EXTEND_MVT_v8i32_r(RetVT, Op0, Op0IsKill);
[all …]
DX86GenCallingConv.inc242 LocVT == MVT::v8i32 ||
915 LocVT == MVT::v8i32 ||
1008 LocVT == MVT::v8i32 ||
1137 LocVT == MVT::v8i32 ||
1185 LocVT == MVT::v8i32 ||
1249 LocVT == MVT::v8i32 ||
1562 LocVT == MVT::v8i32 ||
1628 LocVT == MVT::v8i32 ||
1699 LocVT == MVT::v8i32 ||
1987 LocVT == MVT::v8i32 ||
[all …]
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
312 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
313 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
314 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
315 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
610 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 }, in getCmpSelInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp229 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
230 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
240 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
260 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
261 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td549 def SGPR_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256Regs)> {
553 def TTMP_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add TTMP_256Regs)> {
557 def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
633 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32,
DSIInstructions.td898 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
901 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
1048 def : BitConvert <v8i32, v8f32, SReg_256>;
1049 def : BitConvert <v8f32, v8i32, SReg_256>;
1050 def : BitConvert <v8i32, v8f32, VReg_256>;
1051 def : BitConvert <v8f32, v8i32, VReg_256>;
1427 defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">;
DAMDGPUCallingConv.td125 CCIfType<[v8i32, v8f32], CCAssignToStack<32, 4>>,
DSMInstructions.td808 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
814 defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX8", v8i32>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td72 def v8i32 : ValueType<256, 48>; // 8 x i32 vector value
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp193 case MVT::v8i32: return VectorType::get(Type::getInt32Ty(Context), 8); in getTypeForEVT()
/third_party/mesa3d/src/amd/llvm/
Dac_llvm_build.h94 LLVMTypeRef v8i32; member
/third_party/mesa3d/src/amd/vulkan/
Dradv_nir_to_llvm.c340 LLVMValueRef descriptor1 = radv_load_rsrc(ctx, plane1_addr, ctx->ac.v8i32); in radv_get_sampler_desc()
353 return radv_load_rsrc(ctx, index, v4 ? ctx->ac.v4i32 : ctx->ac.v8i32); in radv_get_sampler_desc()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_llvm_ps.c70 LLVMBuildPointerCast(ctx->ac.builder, ptr, ac_array_in_const32_addr_space(ctx->ac.v8i32), ""); in si_nir_emit_fbfetch()

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