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Searched refs:vs_state (Results 1 – 16 of 16) sorted by relevance

/third_party/mesa3d/src/amd/vulkan/
Dradv_device_generated_commands.c1212 const struct radv_vs_input_state *vs_state = in radv_prepare_dgc() local
1219 vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i] in radv_prepare_dgc()
1222 … vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i] : graphics_pipeline->attrib_ends[i]; in radv_prepare_dgc()
1226 (vs_state ? vs_state->offsets[i] << 16 : 0) | in radv_prepare_dgc()
1231 params.vbo_cnt = idx | (vs_state ? DGC_DYNAMIC_VERTEX_INPUT : 0); in radv_prepare_dgc()
Dradv_cmd_buffer.c3708 const struct radv_vs_input_state *vs_state = in radv_write_vertex_descriptors() local
3710 assert(!vs_state || pipeline->use_per_attribute_vb_descs); in radv_write_vertex_descriptors()
3717 vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i] in radv_write_vertex_descriptors()
3723 if (vs_state) { in radv_write_vertex_descriptors()
3724 unsigned format = vs_state->formats[i]; in radv_write_vertex_descriptors()
3728 rsrc_word3 = vs_state->post_shuffle & (1u << i) ? DST_SEL_ZYXW : data_format_dst_sel[dfmt]; in radv_write_vertex_descriptors()
3755 } else if (vs_state) { in radv_write_vertex_descriptors()
3775 if (vs_state) in radv_write_vertex_descriptors()
3776 va += vs_state->offsets[i]; in radv_write_vertex_descriptors()
3786 vs_state ? vs_state->offsets[i] + vs_state->format_sizes[i] : pipeline->attrib_ends[i]; in radv_write_vertex_descriptors()
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/third_party/mesa3d/src/gallium/drivers/r300/
Dr300_flush.c68 r300->vs_state.dirty = FALSE; in r300_flush_and_cleanup()
Dr300_context.h526 struct r300_atom vs_state; member
678 return (struct r300_vertex_shader*)r300->vs_state.state; in r300_vs()
Dr300_state.c1412 r300_mark_atom_dirty(r300, &r300->vs_state); in r300_bind_rs_state()
1993 r300->vs_state.state = NULL; in r300_bind_vs_state()
1996 if (vs == r300->vs_state.state) { in r300_bind_vs_state()
1999 r300->vs_state.state = vs; in r300_bind_vs_state()
2006 r300_mark_atom_dirty(r300, &r300->vs_state); in r300_bind_vs_state()
2007 r300->vs_state.size = vs->shader->code.length + 9 + in r300_bind_vs_state()
Dr300_context.c195 R300_INIT_ATOM(vs_state, 0); in r300_setup_atoms()
Dr300_blit.c68 util_blitter_save_vertex_shader(r300->blitter, r300->vs_state.state); in r300_blitter_begin()
Dr300_state_derived.c1069 if (r300->vs_state.state) { in r300_pick_vertex_shader()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.cpp1212 unsigned vs_state = sctx->current_vs_state; /* all VS bits including LS bits */ in si_emit_vs_state() local
1216 vs_state |= ENCODE_FIELD(VS_STATE_INDEXED, 1); in si_emit_vs_state()
1219 gs_state |= vs_state & in si_emit_vs_state()
1223 if (vs_state != sctx->last_vs_state || in si_emit_vs_state()
1238 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); in si_emit_vs_state()
1250 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, vs_state); in si_emit_vs_state()
1251 radeon_set_sh_reg(tes_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state); in si_emit_vs_state()
1253 radeon_set_sh_reg(vs_base + SI_SGPR_VS_STATE_BITS * 4, NGG ? gs_state : vs_state); in si_emit_vs_state()
1257 sctx->last_vs_state = vs_state; in si_emit_vs_state()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
Dfd6_compute.c48 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in cs_program_emit()
Dfd6_draw.c360 A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in fd6_clear_lrz()
Dfd6_emit.c1249 A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in fd6_emit_restore()
Dfd6_program.c295 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(.vs_state = true, .hs_state = true, in setup_config_stateobj()
/third_party/mesa3d/src/freedreno/vulkan/
Dtu_clear_blit.c719 .vs_state = true, in r3d_common()
Dtu_pipeline.c1696 .vs_state = true, in tu6_emit_program_config()
Dtu_cmd_buffer.c807 .vs_state = true, in tu6_init_hw()