Searched refs:vsew (Results 1 – 4 of 4) sorted by relevance
/third_party/node/deps/v8/src/codegen/riscv64/ |
D | assembler-riscv64.cc | 2869 void Assembler::vsetvli(Register rd, Register rs1, VSew vsew, Vlmul vlmul, in DEFINE_OPIVV() 2871 int32_t zimm = GenZimm(vsew, vlmul, tail, mask); in DEFINE_OPIVV() 2878 void Assembler::vsetivli(Register rd, uint8_t uimm, VSew vsew, Vlmul vlmul, in vsetivli() argument 2881 int32_t zimm = GenZimm(vsew, vlmul, tail, mask) & 0x3FF; in vsetivli() 2895 uint8_t vsew_switch(VSew vsew) { in vsew_switch() argument 2897 switch (vsew) { in vsew_switch() 2914 void Assembler::vl(VRegister vd, Register rs1, uint8_t lumop, VSew vsew, in vl() argument 2916 uint8_t width = vsew_switch(vsew); in vl() 2919 void Assembler::vls(VRegister vd, Register rs1, Register rs2, VSew vsew, in vls() argument 2921 uint8_t width = vsew_switch(vsew); in vls() [all …]
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D | assembler-riscv64.h | 662 static int32_t GenZimm(VSew vsew, Vlmul vlmul, TailAgnosticType tail = tu, 664 return (mask << 7) | (tail << 6) | ((vsew & 0x7) << 3) | (vlmul & 0x7); 667 void vl(VRegister vd, Register rs1, uint8_t lumop, VSew vsew, 669 void vls(VRegister vd, Register rs1, Register rs2, VSew vsew, 671 void vlx(VRegister vd, Register rs1, VRegister vs3, VSew vsew, 674 void vs(VRegister vd, Register rs1, uint8_t sumop, VSew vsew, 676 void vss(VRegister vd, Register rs1, Register rs2, VSew vsew, 678 void vsx(VRegister vd, Register rs1, VRegister vs3, VSew vsew, 681 void vsu(VRegister vd, Register rs1, VRegister vs3, VSew vsew, 694 VRegister vd, Register rs1, uint8_t lumop, VSew vsew, MaskType mask = NoMask [all …]
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D | constants-riscv64.h | 1878 uint32_t vsew = (zimm >> 3) & 0x7; in RvvVsew() local 1879 return vsew; in RvvVsew() 1896 uint32_t vsew = this->RvvVsew(); in RvvSEW() local 1897 switch (vsew) { in RvvSEW()
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/third_party/node/deps/v8/src/execution/riscv64/ |
D | simulator-riscv64.h | 406 uint32_t vsew = rvv_vsew(); in rvv_sew_s() local 407 switch (vsew) { in rvv_sew_s()
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