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/third_party/node/deps/v8/src/regexp/arm64/
Dregexp-macro-assembler-arm64.cc166 __ Ldr(w10, register_location(reg)); in AdvanceRegister()
167 __ Add(w10, w10, by); in AdvanceRegister()
168 __ Str(w10, register_location(reg)); in AdvanceRegister()
213 Pop(w10); in Backtrack()
214 __ Add(x10, code_pointer(), Operand(w10, UXTW)); in Backtrack()
238 __ Add(w10, current_input_offset(), in CheckAtStart()
240 __ Cmp(w10, string_start_minus_one()); in CheckAtStart()
246 __ Add(w10, current_input_offset(), in CheckNotAtStart()
248 __ Cmp(w10, string_start_minus_one()); in CheckNotAtStart()
278 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); in CheckCharacters()
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/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm/crypto/sha/
Dsha256-armv8.S205 eor w10,w20,w20,ror#14
211 eor w16,w16,w10,ror#11 // Sigma1(e)
212 ror w10,w24,#2
219 eor w17,w10,w17,ror#13 // Sigma0(a)
226 ldp w9,w10,[x1],#2*4
273 rev w10,w10 // 7
282 add w20,w20,w10 // h+=X[i]
478 str w10,[sp,#12]
485 ror w10,w21,#2
492 eor w10,w10,w21,ror#13
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Dsha1-armv8.S126 add w22,w22,w10 // future e+=X[i]
285 eor w8,w8,w10
310 eor w10,w10,w12
314 eor w10,w10,w19
318 eor w10,w10,w7
321 ror w10,w10,#31
331 add w21,w21,w10 // future e+=X[i]
354 eor w13,w13,w10
410 eor w19,w19,w10
478 eor w8,w8,w10
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/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm_avx2/crypto/sha/
Dsha256-armv8.S205 eor w10,w20,w20,ror#14
211 eor w16,w16,w10,ror#11 // Sigma1(e)
212 ror w10,w24,#2
219 eor w17,w10,w17,ror#13 // Sigma0(a)
226 ldp w9,w10,[x1],#2*4
273 rev w10,w10 // 7
282 add w20,w20,w10 // h+=X[i]
478 str w10,[sp,#12]
485 ror w10,w21,#2
492 eor w10,w10,w21,ror#13
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Dsha1-armv8.S126 add w22,w22,w10 // future e+=X[i]
285 eor w8,w8,w10
310 eor w10,w10,w12
314 eor w10,w10,w19
318 eor w10,w10,w7
321 ror w10,w10,#31
331 add w21,w21,w10 // future e+=X[i]
354 eor w13,w13,w10
410 eor w19,w19,w10
478 eor w8,w8,w10
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/third_party/node/deps/openssl/config/archs/linux-aarch64/asm/crypto/sha/
Dsha256-armv8.S205 eor w10,w20,w20,ror#14
211 eor w16,w16,w10,ror#11 // Sigma1(e)
212 ror w10,w24,#2
219 eor w17,w10,w17,ror#13 // Sigma0(a)
226 ldp w9,w10,[x1],#2*4
273 rev w10,w10 // 7
282 add w20,w20,w10 // h+=X[i]
478 str w10,[sp,#12]
485 ror w10,w21,#2
492 eor w10,w10,w21,ror#13
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Dsha1-armv8.S126 add w22,w22,w10 // future e+=X[i]
285 eor w8,w8,w10
310 eor w10,w10,w12
314 eor w10,w10,w19
318 eor w10,w10,w7
321 ror w10,w10,#31
331 add w21,w21,w10 // future e+=X[i]
354 eor w13,w13,w10
410 eor w19,w19,w10
478 eor w8,w8,w10
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/third_party/node/deps/openssl/config/archs/linux-aarch64/asm_avx2/crypto/sha/
Dsha256-armv8.S205 eor w10,w20,w20,ror#14
211 eor w16,w16,w10,ror#11 // Sigma1(e)
212 ror w10,w24,#2
219 eor w17,w10,w17,ror#13 // Sigma0(a)
226 ldp w9,w10,[x1],#2*4
273 rev w10,w10 // 7
282 add w20,w20,w10 // h+=X[i]
478 str w10,[sp,#12]
485 ror w10,w21,#2
492 eor w10,w10,w21,ror#13
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Dsha1-armv8.S126 add w22,w22,w10 // future e+=X[i]
285 eor w8,w8,w10
310 eor w10,w10,w12
314 eor w10,w10,w19
318 eor w10,w10,w7
321 ror w10,w10,#31
331 add w21,w21,w10 // future e+=X[i]
354 eor w13,w13,w10
410 eor w19,w19,w10
478 eor w8,w8,w10
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/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm_avx2/crypto/chacha/
Dchacha-armv8.S83 add w6,w6,w10
99 eor w10,w10,w14
103 ror w10,w10,#20
107 add w6,w6,w10
123 eor w10,w10,w14
127 ror w10,w10,#25
130 add w5,w5,w10
146 eor w10,w10,w15
150 ror w10,w10,#20
154 add w5,w5,w10
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/third_party/node/deps/openssl/config/archs/darwin64-arm64-cc/asm/crypto/chacha/
Dchacha-armv8.S83 add w6,w6,w10
99 eor w10,w10,w14
103 ror w10,w10,#20
107 add w6,w6,w10
123 eor w10,w10,w14
127 ror w10,w10,#25
130 add w5,w5,w10
146 eor w10,w10,w15
150 ror w10,w10,#20
154 add w5,w5,w10
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/third_party/node/deps/openssl/config/archs/linux-aarch64/asm/crypto/chacha/
Dchacha-armv8.S83 add w6,w6,w10
99 eor w10,w10,w14
103 ror w10,w10,#20
107 add w6,w6,w10
123 eor w10,w10,w14
127 ror w10,w10,#25
130 add w5,w5,w10
146 eor w10,w10,w15
150 ror w10,w10,#20
154 add w5,w5,w10
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/third_party/node/deps/openssl/config/archs/linux-aarch64/asm_avx2/crypto/chacha/
Dchacha-armv8.S83 add w6,w6,w10
99 eor w10,w10,w14
103 ror w10,w10,#20
107 add w6,w6,w10
123 eor w10,w10,w14
127 ror w10,w10,#25
130 add w5,w5,w10
146 eor w10,w10,w15
150 ror w10,w10,#20
154 add w5,w5,w10
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/third_party/ffmpeg/libswscale/aarch64/
Dhscale.S121 ldp w10, w11, [x5, #8] // filterPos[idx + 2], [idx + 3]
129 ldr w10, [x3, w10, UXTW] // src[filterPos[idx + 2]][0..3]
136 …stp w10, w11, [sp, #8] // *scratch_mem = { src[filterPos[idx + 2]][0..3],…
145 …ldp w10, w11, [x5, #8] // filterPos[idx + 2][0..3], [idx + 3][0..3], next…
163 ldr w10, [x3, w10, UXTW] // src[filterPos[idx + 2]], next iteration
178 …stp w10, w11, [sp, #8] // *scratch_mem = { src[filterPos[idx + 2]][0..3],…
Dyuv2rgb_neon.S26 ldp w9, w10, [sp, #\yoff]
29 ldr w10, [sp, #\ycoeff]
37 dup v0.8H, w10
55 dup v0.8H, w10
71 dup v0.8H, w10
Drgb2rgb_neon.S63 ldrb w10, [x1], #1
65 bfi w9, w10, #8, #8
/third_party/openh264/codec/encoder/core/arm64/
Dsvc_motion_estimation_aarch64_neon.S123 ldrh w10, [x9] // sum of last line of pFeatureOfBlock[i]
136 subs w10, w10, w12
138 add w0, w10, w11
202 ldrh w10, [x9] // sum of last line of pFeatureOfBlock[i]
214 subs w10, w10, w12
216 add w0, w10, w11
Dintra_pred_sad_3_opt_aarch64_neon.S405 mov w10, w0
406 SELECT_BEST_COST_PREFER_HIGHER w10
410 sub w9, w10, w2
417 sub w8, w10, w1
432 mov w0, w10
/third_party/ffmpeg/libavfilter/aarch64/
Dvf_nlmeans_neon.S43 1: mov w10, w6 // width copy for each line
71 subs w10, w10, #16 // width dec
/third_party/ffmpeg/libavcodec/aarch64/
Dh264cmc_neon.S37 lsr w10, w4, #1
39 lsl w10, w10, #1
40 add w9, w9, w10
207 lsr w10, w4, #1
209 lsl w10, w10, #1
210 add w9, w9, w10
Dhevcdsp_sao_neon.S44 add w10, w8, w5 // k + sao_left_class
45 and w10, w10, #0x1F
/third_party/vixl/doc/aarch64/topics/
Dextending-the-disassembler.md52 VIXL disasm 0x7fff04cb05f0: tbz w10, #2, #-0x10 (addr 0x7fff04cb05e0)
53 custom disasm 0x8: tbz w10, #2, #-0x10 (addr -0x8)
/third_party/openh264/codec/processing/src/arm64/
Ddown_sample_aarch64_neon.S229 mov w10, #32767
230 and w8, w6, w10
238 and w9, w7, w10
/third_party/FreeBSD/lib/msun/ld128/
De_lgammal_r.c174 w10 = -1.39240539108367641920172649259736394e+00L, variable
320 y*(w9+y*(w10+y*(w11+y*(w12+y*(w13+y*(w14+y*(w15+y*(w16+ in lgammal_r()
/third_party/vixl/test/aarch64/
Dtest-disasm-aarch64.cc80 COMPARE_MACRO(Mov(w10, Operand(w11, UXTB)), "uxtb w10, w11"); in TEST()
541 COMPARE(uxtb(w10, w11), "uxtb w10, w11"); in TEST()
558 COMPARE(bfi(w9, w10, 5, 16), "bfi w9, w10, #5, #16"); in TEST()
591 COMPARE(crc32b(w10, w20, w30), "crc32b w10, w20, w30"); in TEST()
953 COMPARE_PREFIX(tbnz(w10, 31, INST_OFF(0)), "tbnz w10, #31, #+0x0"); in TEST()
1132 COMPARE(ldrb(w10, MemOperand(x11, 255, PostIndex)), "ldrb w10, [x11], #255"); in TEST()
1169 COMPARE(ldrh(w10, MemOperand(x11, 255, PostIndex)), "ldrh w10, [x11], #255"); in TEST()
1278 COMPARE(ldrsh(w10, MemOperand(x11, -6)), "ldursh w10, [x11, #-6]"); in TEST()
1373 COMPARE(ldrsh(w10, MemOperand(x11, -6), option), "ldursh w10, [x11, #-6]"); in TEST()
1581 COMPARE(stxrh(w10, w11, MemOperand(x12)), "stxrh w10, w11, [x12]"); in TEST()
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