Searched refs:DppCtrl (Results 1 – 4 of 4) sorted by relevance
702 if (Imm <= DppCtrl::QUAD_PERM_LAST) { in printDPPCtrl()708 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && in printDPPCtrl()709 (Imm <= DppCtrl::ROW_SHL_LAST)) { in printDPPCtrl()712 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && in printDPPCtrl()713 (Imm <= DppCtrl::ROW_SHR_LAST)) { in printDPPCtrl()716 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && in printDPPCtrl()717 (Imm <= DppCtrl::ROW_ROR_LAST)) { in printDPPCtrl()720 } else if (Imm == DppCtrl::WAVE_SHL1) { in printDPPCtrl()726 } else if (Imm == DppCtrl::WAVE_ROL1) { in printDPPCtrl()732 } else if (Imm == DppCtrl::WAVE_SHR1) { in printDPPCtrl()[all …]
6438 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || in isDPPCtrl()6439 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || in isDPPCtrl()6440 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || in isDPPCtrl()6441 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || in isDPPCtrl()6442 (Imm == DppCtrl::WAVE_SHL1) || in isDPPCtrl()6443 (Imm == DppCtrl::WAVE_ROL1) || in isDPPCtrl()6444 (Imm == DppCtrl::WAVE_SHR1) || in isDPPCtrl()6445 (Imm == DppCtrl::WAVE_ROR1) || in isDPPCtrl()6446 (Imm == DppCtrl::ROW_MIRROR) || in isDPPCtrl()6447 (Imm == DppCtrl::ROW_HALF_MIRROR) || in isDPPCtrl()[all …]
3703 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || in verifyInstruction()3704 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || in verifyInstruction()3705 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || in verifyInstruction()3706 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || in verifyInstruction()3707 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || in verifyInstruction()3708 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || in verifyInstruction()3709 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { in verifyInstruction()3713 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && in verifyInstruction()3719 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && in verifyInstruction()3725 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST && in verifyInstruction()
448 enum DppCtrl : unsigned { enum