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Searched refs:NVISA_GV100_CHIPSET (Results 1 – 6 of 6) sorted by relevance

/third_party/mesa3d/src/nouveau/codegen/
Dnv50_ir_from_nir.cpp3306 op.lower_fdiv = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()
3313 op.lower_flrp16 = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()
3322 …op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHI… in nvir_nir_shader_compiler_options()
3324 …op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIP… in nvir_nir_shader_compiler_options()
3338 op.lower_isign = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()
3339 op.lower_fsign = (chipset >= NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()
3382 op.lower_rotate = (chipset < NVISA_GV100_CHIPSET); in nvir_nir_shader_compiler_options()
3392 … ((chipset >= NVISA_GV100_CHIPSET && shader_type == PIPE_SHADER_FRAGMENT) ? nir_var_shader_in : 0) in nvir_nir_shader_compiler_options()
3397 ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_imul64 : 0) | in nvir_nir_shader_compiler_options()
3398 ((chipset >= NVISA_GV100_CHIPSET) ? nir_lower_isign64 : 0) | in nvir_nir_shader_compiler_options()
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Dnv50_ir_driver.h79 #define NVISA_GV100_CHIPSET 0x140 macro
Dnv50_ir_target_nvc0.cpp270 const unsigned int bs = (chipset >= NVISA_GV100_CHIPSET) ? 16 : 0; in getFileSize()
Dnv50_ir_lowering_nvc0.cpp902 if (prog->getTarget()->getChipset() >= NVISA_GV100_CHIPSET) in visit()
1742 targ->getChipset() < NVISA_GV100_CHIPSET) { in handleCasExch()
Dnv50_ir_ra.cpp2364 if (targ->getChipset() < NVISA_GV100_CHIPSET) { in texConstraintGM107()
/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_program.c688 if (info_out.target >= NVISA_GV100_CHIPSET) in nvc0_program_translate()