Searched refs:ctx_reg (Results 1 – 5 of 5) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_shaders.cpp | 939 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2, in si_emit_shader_gs()
940 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3); in si_emit_shader_gs()
945 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize); in si_emit_shader_gs()
949 shader->ctx_reg.gs.vgt_gs_max_vert_out); in si_emit_shader_gs()
955 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1, in si_emit_shader_gs()
956 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3); in si_emit_shader_gs()
960 shader->ctx_reg.gs.vgt_gs_instance_cnt); in si_emit_shader_gs()
965 shader->ctx_reg.gs.vgt_gs_onchip_cntl); in si_emit_shader_gs()
969 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup); in si_emit_shader_gs()
973 shader->ctx_reg.gs.vgt_esgs_ring_itemsize); in si_emit_shader_gs()
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| D | si_shader.h | 950 } ctx_reg; member
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| D | si_state_draw.cpp | 238 key.index |= si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ctx_reg.ngg.vgt_stages.index; in si_update_shaders()
262 unsigned db_shader_control = sctx->shader.ps.current->ctx_reg.ps.db_shader_control; in si_update_shaders()
273 … sctx->atoms.s.spi_map.emit = sctx->emit_spi_map[sctx->shader.ps.current->ctx_reg.ps.num_interp]; in si_update_shaders()
1343 unsigned vgt_gs_onchip_cntl = sctx->shader.gs.current->ctx_reg.gs.vgt_gs_onchip_cntl; in gfx10_emit_ge_cntl()
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| /third_party/skia/third_party/externals/libwebp/src/dsp/ |
| D | cost_mips_dsp_r2.c | 20 int v_reg, ctx_reg; in GetResidualCost_MIPSdspR2() local
71 [ctx_reg]"=&r"(ctx_reg), [p_costs]"+&r"(p_costs), [temp0]"=&r"(temp0), in GetResidualCost_MIPSdspR2()
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| D | cost_mips32.c | 20 int v_reg, ctx_reg; in GetResidualCost_MIPS32() local
76 [ctx_reg]"=&r"(ctx_reg), [p_costs]"+&r"(p_costs), [temp0]"=&r"(temp0), in GetResidualCost_MIPS32()
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