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Searched refs:max_render_backends (Results 1 – 21 of 21) sorted by relevance

/third_party/mesa3d/src/amd/common/
Dac_surface_test_common.h45 info->max_render_backends = 16; in init_vega10()
60 info->max_render_backends = 16; in init_vega20()
76 info->max_render_backends = 2; in init_raven()
91 info->max_render_backends = 1; in init_raven2()
216 info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1; in get_radeon_info()
Dac_gpu_info.c949 info->max_render_backends = device_info.num_rb_pipes; in ac_query_gpu_info()
952 info->max_render_backends = 2; in ac_query_gpu_info()
1214 if (info->max_render_backends == 1 && info->gfx_level == GFX9) in ac_query_gpu_info()
1298 info->max_render_backends; in ac_query_gpu_info()
1576 fprintf(f, " max_render_backends = %i\n", info->max_render_backends); in ac_print_gpu_info()
1756 unsigned num_rb = MIN2(info->max_render_backends, 16); in ac_get_harvested_configs()
Dac_gpu_info.h226 uint32_t max_render_backends; /* number of render backends incl. disabled ones */ member
Dac_surface.c300 if (info->max_render_backends == 1) { in ac_get_supported_modifiers()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_binning.c47 util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se); in si_find_bin_size()
312 const unsigned num_rbs = sctx->screen->info.max_render_backends; in gfx10_get_bin_sizes()
466 if (sscreen->info.max_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && in si_emit_dpbb_state()
Dsi_query.c471 result->u32 = sctx->screen->info.max_render_backends; in si_query_sw_get_result()
619 unsigned max_rbs = screen->info.max_render_backends; in si_query_hw_prepare_buffer()
711 query->result_size = 16 * sscreen->info.max_render_backends; in si_query_hw_create()
817 uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends); in si_query_hw_do_emit_start()
947 fence_va = va + sctx->screen->info.max_render_backends * 16 - 8; in si_query_hw_do_emit_stop()
1280 unsigned max_rbs = sctx->screen->info.max_render_backends; in si_get_hw_query_params()
1363 unsigned max_rbs = sscreen->info.max_render_backends; in si_query_hw_add_result()
Dsi_fence.c105 16 * sscreen->info.max_render_backends, 256); in si_cp_release_mem()
110 assert(16 * ctx->screen->info.max_render_backends <= scratch->b.b.width0); in si_cp_release_mem()
Dsi_pipe.c500 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256); in si_create_context()
1307 sscreen->info.max_render_backends >= 2 && in radeonsi_screen_create_impl()
1340 if (sscreen->info.max_render_backends > 4) { in radeonsi_screen_create_impl()
Dsi_state.c5523 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16); in si_set_raster_config()
5799 if (sscreen->info.max_render_backends <= 4) { in si_init_cs_preamble_state()
/third_party/mesa3d/src/gallium/drivers/r600/
Dr600_query.c433 result->u32 = rctx->screen->info.max_render_backends; in r600_query_sw_get_result()
540 unsigned max_rbs = rscreen->info.max_render_backends; in r600_query_hw_prepare_buffer()
625 query->result_size = 16 * rscreen->info.max_render_backends; in r600_query_hw_create()
824 fence_va = va + ctx->screen->info.max_render_backends * 16 - 8; in r600_query_hw_do_emit_stop()
1085 unsigned max_rbs = rctx->screen->info.max_render_backends; in r600_get_hw_query_params()
1176 unsigned max_rbs = rscreen->info.max_render_backends; in r600_query_hw_add_result()
1848 ctx->screen->info.max_render_backends = 8; in r600_query_fix_enabled_rb_mask()
1850 max_rbs = ctx->screen->info.max_render_backends; in r600_query_fix_enabled_rb_mask()
2120 if (((struct r600_common_screen*)rctx->b.screen)->info.max_render_backends > 0) in r600_query_init()
Dr600_pipe_common.c1322 printf("num_render_backends = %i\n", rscreen->info.max_render_backends); in r600_common_screen_init()
/third_party/mesa3d/src/amd/vulkan/winsys/null/
Dradv_null_winsys.c136 info->max_render_backends = gpu_info[info->family].num_render_backends; in radv_null_winsys_query_info()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_winsys.c398 &ws->info.max_render_backends)) in do_winsys_init()
438 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends); in do_winsys_init()
/third_party/mesa3d/src/amd/vulkan/
Dradv_query.c116 unsigned db_count = device->physical_device->rad_info.max_render_backends; in build_occlusion_query_shader()
1101 pool->stride = 16 * device->physical_device->rad_info.max_render_backends; in radv_CreateQueryPool()
1228 uint32_t db_count = device->physical_device->rad_info.max_render_backends; in radv_GetQueryPoolResults()
1776 BITFIELD64_MASK(cmd_buffer->device->physical_device->rad_info.max_render_backends); in emit_begin_query()
Dradv_shader.c1237 unsigned max_render_backends = pdevice->rad_info.max_render_backends; in radv_consider_culling() local
1240 if (max_render_backends / max_se == 4) in radv_consider_culling()
Dsi_cmd_buffer.c178 unsigned num_rb = MIN2(physical_device->rad_info.max_render_backends, 16); in si_set_raster_config()
433 if (physical_device->rad_info.max_render_backends <= 4) { in si_emit_graphics()
Dradv_pipeline.c5296 util_logbase2_ceil(pdevice->rad_info.max_render_backends / pdevice->rad_info.max_se); in radv_gfx9_compute_bin_size()
5356 const unsigned rb_count = pdevice->rad_info.max_render_backends; in radv_gfx10_compute_bin_size()
5465 if (pdev->rad_info.max_render_backends > 4) { in radv_get_binning_settings()
Dradv_device.c825 device->use_ngg_culling = device->use_ngg && device->rad_info.max_render_backends > 1 && in radv_physical_device_try_create()
Dradv_cmd_buffer.c555 unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends; in radv_reset_cmd_buffer()
/third_party/mesa3d/docs/relnotes/
D21.0.0.rst2065 - ac: rename num_render_backends -\> max_render_backends
D22.0.0.rst3684 - radv: fix max_render_backends for Sienna Cichlid null winsys