Searched refs:util_last_bit64 (Results 1 – 17 of 17) sorted by relevance
132 assert(util_last_bit64(num) <= num_bits); in rogue_encoder_reg()133 assert(util_last_bit64(bank) <= bank_bits); in rogue_encoder_reg()
58 assert(util_last_bit64(source) <= total_bits_left && in rogue_distribute_value()
242 util_last_bit64(uint64_t u) in util_last_bit64() function
543 return 64 - util_last_bit64(a); in _mesa_count_leading_zeros64()
121 unsigned copy_size = 1u << MIN2(util_last_bit64(remaining) - 1, 4); in lower_memcpy_impl()
1551 res = bitmask(util_last_bit64(src0)) & bitmask(util_last_bit64(src1)); in nir_unsigned_upper_bound()1555 res = bitmask(util_last_bit64(src0)) | bitmask(util_last_bit64(src1)); in nir_unsigned_upper_bound()1558 if (util_last_bit64(src0) + src1 > scalar.def->bit_size) in nir_unsigned_upper_bound()
69 return util_last_bit64(ctx->shader->selector->info.outputs_written) * 4; in get_tcs_out_vertex_dw_stride_constant()77 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->info.patch_outputs_written); in get_tcs_out_patch_stride()
521 unsigned num_outputs = util_last_bit64(shader->selector->info.outputs_written); in si_init_shader_args()528 unsigned num_inputs = util_last_bit64(shader->previous_stage_sel->info.outputs_written); in si_init_shader_args()1538 util_last_bit64(sel->info.outputs_written), in si_lower_io_to_mem()1539 util_last_bit64(sel->info.patch_outputs_written), in si_lower_io_to_mem()
780 info->esgs_itemsize = util_last_bit64(info->outputs_written) * 16; in si_nir_scan_shader()
656 unsigned num_tcs_outputs = util_last_bit64(tcs->info.outputs_written); in si_emit_derived_tess_state()658 unsigned num_tcs_patch_outputs = util_last_bit64(tcs->info.patch_outputs_written); in si_emit_derived_tess_state()
931 int max_outputs = util_last_bit64(c->prog->info.outputs_written); in setup_registers_and_variables()
596 unsigned msb = util_last_bit64(size); /* 0 = no bit is set */ in radv_amdgpu_get_optimal_vm_alignment()
143 mask &= ~BITFIELD64_BIT(util_last_bit64(mask) - 1); in allocate_inline_push_consts()
3562 if (mask == u_bit_consecutive64(base, util_last_bit64(mask) - base)) { in radv_emit_all_inline_push_consts()
518 nir->num_inputs = util_last_bit64(nir->info.inputs_read); in lvp_shader_compile_to_ir()
4562 num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask); in evergreen_setup_tess_constants()4565 num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask); in evergreen_setup_tess_constants()4567 num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask); in evergreen_setup_tess_constants()
734 uint32_t last_output = util_last_bit64(nir->info.outputs_written); in update_psiz_location()