1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <string.h>
25 #include <stdarg.h>
26
27 #include "brw_eu_defines.h"
28 #include "brw_inst.h"
29 #include "brw_shader.h"
30 #include "brw_reg.h"
31 #include "brw_inst.h"
32 #include "brw_eu.h"
33 #include "util/half_float.h"
34
35 bool
brw_has_jip(const struct intel_device_info * devinfo,enum opcode opcode)36 brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode)
37 {
38 if (devinfo->ver < 6)
39 return false;
40
41 return opcode == BRW_OPCODE_IF ||
42 opcode == BRW_OPCODE_ELSE ||
43 opcode == BRW_OPCODE_ENDIF ||
44 opcode == BRW_OPCODE_WHILE ||
45 opcode == BRW_OPCODE_BREAK ||
46 opcode == BRW_OPCODE_CONTINUE ||
47 opcode == BRW_OPCODE_HALT;
48 }
49
50 bool
brw_has_uip(const struct intel_device_info * devinfo,enum opcode opcode)51 brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode)
52 {
53 if (devinfo->ver < 6)
54 return false;
55
56 return (devinfo->ver >= 7 && opcode == BRW_OPCODE_IF) ||
57 (devinfo->ver >= 8 && opcode == BRW_OPCODE_ELSE) ||
58 opcode == BRW_OPCODE_BREAK ||
59 opcode == BRW_OPCODE_CONTINUE ||
60 opcode == BRW_OPCODE_HALT;
61 }
62
63 static bool
has_branch_ctrl(const struct intel_device_info * devinfo,enum opcode opcode)64 has_branch_ctrl(const struct intel_device_info *devinfo, enum opcode opcode)
65 {
66 if (devinfo->ver < 8)
67 return false;
68
69 return opcode == BRW_OPCODE_IF ||
70 opcode == BRW_OPCODE_ELSE;
71 /* opcode == BRW_OPCODE_GOTO; */
72 }
73
74 static bool
is_logic_instruction(unsigned opcode)75 is_logic_instruction(unsigned opcode)
76 {
77 return opcode == BRW_OPCODE_AND ||
78 opcode == BRW_OPCODE_NOT ||
79 opcode == BRW_OPCODE_OR ||
80 opcode == BRW_OPCODE_XOR;
81 }
82
83 static bool
is_send(unsigned opcode)84 is_send(unsigned opcode)
85 {
86 return opcode == BRW_OPCODE_SEND ||
87 opcode == BRW_OPCODE_SENDC ||
88 opcode == BRW_OPCODE_SENDS ||
89 opcode == BRW_OPCODE_SENDSC;
90 }
91
92 static bool
is_split_send(UNUSED const struct intel_device_info * devinfo,unsigned opcode)93 is_split_send(UNUSED const struct intel_device_info *devinfo, unsigned opcode)
94 {
95 if (devinfo->ver >= 12)
96 return is_send(opcode);
97 else
98 return opcode == BRW_OPCODE_SENDS ||
99 opcode == BRW_OPCODE_SENDSC;
100 }
101
102 const char *const conditional_modifier[16] = {
103 [BRW_CONDITIONAL_NONE] = "",
104 [BRW_CONDITIONAL_Z] = ".z",
105 [BRW_CONDITIONAL_NZ] = ".nz",
106 [BRW_CONDITIONAL_G] = ".g",
107 [BRW_CONDITIONAL_GE] = ".ge",
108 [BRW_CONDITIONAL_L] = ".l",
109 [BRW_CONDITIONAL_LE] = ".le",
110 [BRW_CONDITIONAL_R] = ".r",
111 [BRW_CONDITIONAL_O] = ".o",
112 [BRW_CONDITIONAL_U] = ".u",
113 };
114
115 static const char *const m_negate[2] = {
116 [0] = "",
117 [1] = "-",
118 };
119
120 static const char *const _abs[2] = {
121 [0] = "",
122 [1] = "(abs)",
123 };
124
125 static const char *const m_bitnot[2] = { "", "~" };
126
127 static const char *const vert_stride[16] = {
128 [0] = "0",
129 [1] = "1",
130 [2] = "2",
131 [3] = "4",
132 [4] = "8",
133 [5] = "16",
134 [6] = "32",
135 [15] = "VxH",
136 };
137
138 static const char *const width[8] = {
139 [0] = "1",
140 [1] = "2",
141 [2] = "4",
142 [3] = "8",
143 [4] = "16",
144 };
145
146 static const char *const horiz_stride[4] = {
147 [0] = "0",
148 [1] = "1",
149 [2] = "2",
150 [3] = "4"
151 };
152
153 static const char *const chan_sel[4] = {
154 [0] = "x",
155 [1] = "y",
156 [2] = "z",
157 [3] = "w",
158 };
159
160 static const char *const debug_ctrl[2] = {
161 [0] = "",
162 [1] = ".breakpoint"
163 };
164
165 static const char *const saturate[2] = {
166 [0] = "",
167 [1] = ".sat"
168 };
169
170 static const char *const cmpt_ctrl[2] = {
171 [0] = "",
172 [1] = "compacted"
173 };
174
175 static const char *const accwr[2] = {
176 [0] = "",
177 [1] = "AccWrEnable"
178 };
179
180 static const char *const branch_ctrl[2] = {
181 [0] = "",
182 [1] = "BranchCtrl"
183 };
184
185 static const char *const wectrl[2] = {
186 [0] = "",
187 [1] = "WE_all"
188 };
189
190 static const char *const exec_size[8] = {
191 [0] = "1",
192 [1] = "2",
193 [2] = "4",
194 [3] = "8",
195 [4] = "16",
196 [5] = "32"
197 };
198
199 static const char *const pred_inv[2] = {
200 [0] = "+",
201 [1] = "-"
202 };
203
204 const char *const pred_ctrl_align16[16] = {
205 [1] = "",
206 [2] = ".x",
207 [3] = ".y",
208 [4] = ".z",
209 [5] = ".w",
210 [6] = ".any4h",
211 [7] = ".all4h",
212 };
213
214 static const char *const pred_ctrl_align1[16] = {
215 [BRW_PREDICATE_NORMAL] = "",
216 [BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
217 [BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
218 [BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
219 [BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
220 [BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
221 [BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
222 [BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
223 [BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
224 [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
225 [BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
226 [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
227 [BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h",
228 };
229
230 static const char *const thread_ctrl[4] = {
231 [BRW_THREAD_NORMAL] = "",
232 [BRW_THREAD_ATOMIC] = "atomic",
233 [BRW_THREAD_SWITCH] = "switch",
234 };
235
236 static const char *const compr_ctrl[4] = {
237 [0] = "",
238 [1] = "sechalf",
239 [2] = "compr",
240 [3] = "compr4",
241 };
242
243 static const char *const dep_ctrl[4] = {
244 [0] = "",
245 [1] = "NoDDClr",
246 [2] = "NoDDChk",
247 [3] = "NoDDClr,NoDDChk",
248 };
249
250 static const char *const mask_ctrl[4] = {
251 [0] = "",
252 [1] = "nomask",
253 };
254
255 static const char *const access_mode[2] = {
256 [0] = "align1",
257 [1] = "align16",
258 };
259
260 static const char *const reg_file[4] = {
261 [0] = "A",
262 [1] = "g",
263 [2] = "m",
264 [3] = "imm",
265 };
266
267 static const char *const writemask[16] = {
268 [0x0] = ".",
269 [0x1] = ".x",
270 [0x2] = ".y",
271 [0x3] = ".xy",
272 [0x4] = ".z",
273 [0x5] = ".xz",
274 [0x6] = ".yz",
275 [0x7] = ".xyz",
276 [0x8] = ".w",
277 [0x9] = ".xw",
278 [0xa] = ".yw",
279 [0xb] = ".xyw",
280 [0xc] = ".zw",
281 [0xd] = ".xzw",
282 [0xe] = ".yzw",
283 [0xf] = "",
284 };
285
286 static const char *const end_of_thread[2] = {
287 [0] = "",
288 [1] = "EOT"
289 };
290
291 /* SFIDs on Gfx4-5 */
292 static const char *const gfx4_sfid[16] = {
293 [BRW_SFID_NULL] = "null",
294 [BRW_SFID_MATH] = "math",
295 [BRW_SFID_SAMPLER] = "sampler",
296 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
297 [BRW_SFID_DATAPORT_READ] = "read",
298 [BRW_SFID_DATAPORT_WRITE] = "write",
299 [BRW_SFID_URB] = "urb",
300 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
301 [BRW_SFID_VME] = "vme",
302 };
303
304 static const char *const gfx6_sfid[16] = {
305 [BRW_SFID_NULL] = "null",
306 [BRW_SFID_MATH] = "math",
307 [BRW_SFID_SAMPLER] = "sampler",
308 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
309 [BRW_SFID_URB] = "urb",
310 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
311 [GFX6_SFID_DATAPORT_SAMPLER_CACHE] = "dp_sampler",
312 [GFX6_SFID_DATAPORT_RENDER_CACHE] = "render",
313 [GFX6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
314 [GFX7_SFID_DATAPORT_DATA_CACHE] = "data",
315 [GFX7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
316 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
317 [HSW_SFID_CRE] = "cre",
318 [GEN_RT_SFID_RAY_TRACE_ACCELERATOR] = "rt accel",
319 [GFX12_SFID_SLM] = "slm",
320 [GFX12_SFID_TGM] = "tgm",
321 [GFX12_SFID_UGM] = "ugm",
322 };
323
324 static const char *const gfx7_gateway_subfuncid[8] = {
325 [BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open",
326 [BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close",
327 [BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg",
328 [BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp",
329 [BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg",
330 [BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state",
331 [BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write",
332 };
333
334 static const char *const gfx4_dp_read_port_msg_type[4] = {
335 [0b00] = "OWord Block Read",
336 [0b01] = "OWord Dual Block Read",
337 [0b10] = "Media Block Read",
338 [0b11] = "DWord Scattered Read",
339 };
340
341 static const char *const g45_dp_read_port_msg_type[8] = {
342 [0b000] = "OWord Block Read",
343 [0b010] = "OWord Dual Block Read",
344 [0b100] = "Media Block Read",
345 [0b110] = "DWord Scattered Read",
346 [0b001] = "Render Target UNORM Read",
347 [0b011] = "AVC Loop Filter Read",
348 };
349
350 static const char *const dp_write_port_msg_type[8] = {
351 [0b000] = "OWord block write",
352 [0b001] = "OWord dual block write",
353 [0b010] = "media block write",
354 [0b011] = "DWord scattered write",
355 [0b100] = "RT write",
356 [0b101] = "streamed VB write",
357 [0b110] = "RT UNORM write", /* G45+ */
358 [0b111] = "flush render cache",
359 };
360
361 static const char *const dp_rc_msg_type_gfx6[16] = {
362 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
363 [GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
364 [GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
365 [GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
366 [GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
367 "OWORD unaligned block read",
368 [GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
369 [GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
370 [GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
371 [GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
372 "OWORD dual block write",
373 [GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
374 [GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
375 "DWORD scattered write",
376 [GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
377 [GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
378 [GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
379 };
380
381 static const char *const dp_rc_msg_type_gfx7[16] = {
382 [GFX7_DATAPORT_RC_MEDIA_BLOCK_READ] = "media block read",
383 [GFX7_DATAPORT_RC_TYPED_SURFACE_READ] = "typed surface read",
384 [GFX7_DATAPORT_RC_TYPED_ATOMIC_OP] = "typed atomic op",
385 [GFX7_DATAPORT_RC_MEMORY_FENCE] = "memory fence",
386 [GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE] = "media block write",
387 [GFX7_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
388 [GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE] = "typed surface write"
389 };
390
391 static const char *const dp_rc_msg_type_gfx9[16] = {
392 [GFX9_DATAPORT_RC_RENDER_TARGET_WRITE] = "RT write",
393 [GFX9_DATAPORT_RC_RENDER_TARGET_READ] = "RT read"
394 };
395
396 static const char *const *
dp_rc_msg_type(const struct intel_device_info * devinfo)397 dp_rc_msg_type(const struct intel_device_info *devinfo)
398 {
399 return (devinfo->ver >= 9 ? dp_rc_msg_type_gfx9 :
400 devinfo->ver >= 7 ? dp_rc_msg_type_gfx7 :
401 devinfo->ver >= 6 ? dp_rc_msg_type_gfx6 :
402 dp_write_port_msg_type);
403 }
404
405 static const char *const m_rt_write_subtype[] = {
406 [0b000] = "SIMD16",
407 [0b001] = "SIMD16/RepData",
408 [0b010] = "SIMD8/DualSrcLow",
409 [0b011] = "SIMD8/DualSrcHigh",
410 [0b100] = "SIMD8",
411 [0b101] = "SIMD8/ImageWrite", /* Gfx6+ */
412 [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
413 };
414
415 static const char *const dp_dc0_msg_type_gfx7[16] = {
416 [GFX7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
417 [GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
418 "DC unaligned OWORD block read",
419 [GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
420 [GFX7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
421 [GFX7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
422 [GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
423 [GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
424 [GFX7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
425 [GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
426 [GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
427 [GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
428 [GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
429 [GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
430 };
431
432 static const char *const dp_oword_block_rw[8] = {
433 [BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW] = "1-low",
434 [BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH] = "1-high",
435 [BRW_DATAPORT_OWORD_BLOCK_2_OWORDS] = "2",
436 [BRW_DATAPORT_OWORD_BLOCK_4_OWORDS] = "4",
437 [BRW_DATAPORT_OWORD_BLOCK_8_OWORDS] = "8",
438 };
439
440 static const char *const dp_dc1_msg_type_hsw[32] = {
441 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
442 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
443 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
444 "DC untyped 4x2 atomic op",
445 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
446 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
447 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
448 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
449 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
450 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
451 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
452 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
453 "DC 4x2 atomic counter op",
454 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
455 [GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ] = "DC A64 scattered read",
456 [GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ] = "DC A64 untyped surface read",
457 [GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP] = "DC A64 untyped atomic op",
458 [GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ] = "DC A64 oword block read",
459 [GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE] = "DC A64 oword block write",
460 [GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE] = "DC A64 untyped surface write",
461 [GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE] = "DC A64 scattered write",
462 [GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP] =
463 "DC untyped atomic float op",
464 [GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP] =
465 "DC A64 untyped atomic float op",
466 [GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP] =
467 "DC A64 untyped atomic half-integer op",
468 [GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP] =
469 "DC A64 untyped atomic half-float op",
470 };
471
472 static const char *const aop[16] = {
473 [BRW_AOP_AND] = "and",
474 [BRW_AOP_OR] = "or",
475 [BRW_AOP_XOR] = "xor",
476 [BRW_AOP_MOV] = "mov",
477 [BRW_AOP_INC] = "inc",
478 [BRW_AOP_DEC] = "dec",
479 [BRW_AOP_ADD] = "add",
480 [BRW_AOP_SUB] = "sub",
481 [BRW_AOP_REVSUB] = "revsub",
482 [BRW_AOP_IMAX] = "imax",
483 [BRW_AOP_IMIN] = "imin",
484 [BRW_AOP_UMAX] = "umax",
485 [BRW_AOP_UMIN] = "umin",
486 [BRW_AOP_CMPWR] = "cmpwr",
487 [BRW_AOP_PREDEC] = "predec",
488 };
489
490 static const char *const aop_float[5] = {
491 [BRW_AOP_FMAX] = "fmax",
492 [BRW_AOP_FMIN] = "fmin",
493 [BRW_AOP_FCMPWR] = "fcmpwr",
494 [BRW_AOP_FADD] = "fadd",
495 };
496
497 static const char * const pixel_interpolator_msg_types[4] = {
498 [GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
499 [GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
500 [GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
501 [GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
502 };
503
504 static const char *const math_function[16] = {
505 [BRW_MATH_FUNCTION_INV] = "inv",
506 [BRW_MATH_FUNCTION_LOG] = "log",
507 [BRW_MATH_FUNCTION_EXP] = "exp",
508 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
509 [BRW_MATH_FUNCTION_RSQ] = "rsq",
510 [BRW_MATH_FUNCTION_SIN] = "sin",
511 [BRW_MATH_FUNCTION_COS] = "cos",
512 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
513 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
514 [BRW_MATH_FUNCTION_POW] = "pow",
515 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
516 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
517 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
518 [GFX8_MATH_FUNCTION_INVM] = "invm",
519 [GFX8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
520 };
521
522 static const char *const sync_function[16] = {
523 [TGL_SYNC_NOP] = "nop",
524 [TGL_SYNC_ALLRD] = "allrd",
525 [TGL_SYNC_ALLWR] = "allwr",
526 [TGL_SYNC_BAR] = "bar",
527 [TGL_SYNC_HOST] = "host",
528 };
529
530 static const char *const math_saturate[2] = {
531 [0] = "",
532 [1] = "sat"
533 };
534
535 static const char *const math_signed[2] = {
536 [0] = "",
537 [1] = "signed"
538 };
539
540 static const char *const math_scalar[2] = {
541 [0] = "",
542 [1] = "scalar"
543 };
544
545 static const char *const math_precision[2] = {
546 [0] = "",
547 [1] = "partial_precision"
548 };
549
550 static const char *const gfx5_urb_opcode[] = {
551 [0] = "urb_write",
552 [1] = "ff_sync",
553 };
554
555 static const char *const gfx7_urb_opcode[] = {
556 [BRW_URB_OPCODE_WRITE_HWORD] = "write HWord",
557 [BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
558 [BRW_URB_OPCODE_READ_HWORD] = "read HWord",
559 [BRW_URB_OPCODE_READ_OWORD] = "read OWord",
560 [GFX7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gfx7+ */
561 [GFX7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gfx7+ */
562 [GFX8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gfx8+ */
563 [GFX8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gfx8+ */
564 [GFX8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gfx8+ */
565 [GFX125_URB_OPCODE_FENCE] = "fence", /* Gfx12.5+ */
566 /* [10-15] - reserved */
567 };
568
569 static const char *const urb_swizzle[4] = {
570 [BRW_URB_SWIZZLE_NONE] = "",
571 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
572 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
573 };
574
575 static const char *const urb_allocate[2] = {
576 [0] = "",
577 [1] = "allocate"
578 };
579
580 static const char *const urb_used[2] = {
581 [0] = "",
582 [1] = "used"
583 };
584
585 static const char *const urb_complete[2] = {
586 [0] = "",
587 [1] = "complete"
588 };
589
590 static const char *const gfx5_sampler_msg_type[] = {
591 [GFX5_SAMPLER_MESSAGE_SAMPLE] = "sample",
592 [GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
593 [GFX5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
594 [GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
595 [GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
596 [GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
597 [GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
598 [GFX5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
599 [GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
600 [GFX5_SAMPLER_MESSAGE_LOD] = "lod",
601 [GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
602 [GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
603 [GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
604 [GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
605 [GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
606 [HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
607 [GFX9_SAMPLER_MESSAGE_SAMPLE_LZ] = "sample_lz",
608 [GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ] = "sample_c_lz",
609 [GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ] = "ld_lz",
610 [GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
611 [GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
612 [GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
613 [GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
614 };
615
616 static const char *const gfx5_sampler_simd_mode[7] = {
617 [BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2",
618 [BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8",
619 [BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
620 [BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64",
621 [GFX10_SAMPLER_SIMD_MODE_SIMD8H] = "SIMD8H",
622 [GFX10_SAMPLER_SIMD_MODE_SIMD16H] = "SIMD16H",
623 };
624
625 static const char *const sampler_target_format[4] = {
626 [0] = "F",
627 [2] = "UD",
628 [3] = "D"
629 };
630
631 static const char *const lsc_operation[] = {
632 [LSC_OP_LOAD] = "load",
633 [LSC_OP_LOAD_CMASK] = "load_cmask",
634 [LSC_OP_STORE] = "store",
635 [LSC_OP_STORE_CMASK] = "store_cmask",
636 [LSC_OP_FENCE] = "fence",
637 [LSC_OP_ATOMIC_INC] = "atomic_inc",
638 [LSC_OP_ATOMIC_DEC] = "atomic_dec",
639 [LSC_OP_ATOMIC_LOAD] = "atomic_load",
640 [LSC_OP_ATOMIC_STORE] = "atomic_store",
641 [LSC_OP_ATOMIC_ADD] = "atomic_add",
642 [LSC_OP_ATOMIC_SUB] = "atomic_sub",
643 [LSC_OP_ATOMIC_MIN] = "atomic_min",
644 [LSC_OP_ATOMIC_MAX] = "atomic_max",
645 [LSC_OP_ATOMIC_UMIN] = "atomic_umin",
646 [LSC_OP_ATOMIC_UMAX] = "atomic_umax",
647 [LSC_OP_ATOMIC_CMPXCHG] = "atomic_cmpxchg",
648 [LSC_OP_ATOMIC_FADD] = "atomic_fadd",
649 [LSC_OP_ATOMIC_FSUB] = "atomic_fsub",
650 [LSC_OP_ATOMIC_FMIN] = "atomic_fmin",
651 [LSC_OP_ATOMIC_FMAX] = "atomic_fmax",
652 [LSC_OP_ATOMIC_FCMPXCHG] = "atomic_fcmpxchg",
653 [LSC_OP_ATOMIC_AND] = "atomic_and",
654 [LSC_OP_ATOMIC_OR] = "atomic_or",
655 [LSC_OP_ATOMIC_XOR] = "atomic_xor",
656 };
657
658 static const char *const lsc_addr_surface_type[] = {
659 [LSC_ADDR_SURFTYPE_FLAT] = "flat",
660 [LSC_ADDR_SURFTYPE_BSS] = "bss",
661 [LSC_ADDR_SURFTYPE_SS] = "ss",
662 [LSC_ADDR_SURFTYPE_BTI] = "bti",
663 };
664
665 static const char* const lsc_fence_scope[] = {
666 [LSC_FENCE_THREADGROUP] = "threadgroup",
667 [LSC_FENCE_LOCAL] = "local",
668 [LSC_FENCE_TILE] = "tile",
669 [LSC_FENCE_GPU] = "gpu",
670 [LSC_FENCE_ALL_GPU] = "all_gpu",
671 [LSC_FENCE_SYSTEM_RELEASE] = "system_release",
672 [LSC_FENCE_SYSTEM_ACQUIRE] = "system_acquire",
673 };
674
675 static const char* const lsc_flush_type[] = {
676 [LSC_FLUSH_TYPE_NONE] = "none",
677 [LSC_FLUSH_TYPE_EVICT] = "evict",
678 [LSC_FLUSH_TYPE_INVALIDATE] = "invalidate",
679 [LSC_FLUSH_TYPE_DISCARD] = "discard",
680 [LSC_FLUSH_TYPE_CLEAN] = "clean",
681 [LSC_FLUSH_TYPE_L3ONLY] = "l3only",
682 [LSC_FLUSH_TYPE_NONE_6] = "none_6",
683 };
684
685 static const char* const lsc_addr_size[] = {
686 [LSC_ADDR_SIZE_A16] = "a16",
687 [LSC_ADDR_SIZE_A32] = "a32",
688 [LSC_ADDR_SIZE_A64] = "a64",
689 };
690
691 static const char* const lsc_backup_fence_routing[] = {
692 [LSC_NORMAL_ROUTING] = "normal_routing",
693 [LSC_ROUTE_TO_LSC] = "route_to_lsc",
694 };
695
696 static const char* const lsc_data_size[] = {
697 [LSC_DATA_SIZE_D8] = "d8",
698 [LSC_DATA_SIZE_D16] = "d16",
699 [LSC_DATA_SIZE_D32] = "d32",
700 [LSC_DATA_SIZE_D64] = "d64",
701 [LSC_DATA_SIZE_D8U32] = "d8u32",
702 [LSC_DATA_SIZE_D16U32] = "d16u32",
703 [LSC_DATA_SIZE_D16BF32] = "d16bf32",
704 };
705
706 static const char* const lsc_vect_size_str[] = {
707 [LSC_VECT_SIZE_V1] = "V1",
708 [LSC_VECT_SIZE_V2] = "V2",
709 [LSC_VECT_SIZE_V3] = "V3",
710 [LSC_VECT_SIZE_V4] = "V4",
711 [LSC_VECT_SIZE_V8] = "V8",
712 [LSC_VECT_SIZE_V16] = "V16",
713 [LSC_VECT_SIZE_V32] = "V32",
714 [LSC_VECT_SIZE_V64] = "V64",
715 };
716
717 static const char* const lsc_cmask_str[] = {
718 [LSC_CMASK_X] = "x",
719 [LSC_CMASK_Y] = "y",
720 [LSC_CMASK_XY] = "xy",
721 [LSC_CMASK_Z] = "z",
722 [LSC_CMASK_XZ] = "xz",
723 [LSC_CMASK_YZ] = "yz",
724 [LSC_CMASK_XYZ] = "xyz",
725 [LSC_CMASK_W] = "w",
726 [LSC_CMASK_XW] = "xw",
727 [LSC_CMASK_YW] = "yw",
728 [LSC_CMASK_XYW] = "xyw",
729 [LSC_CMASK_ZW] = "zw",
730 [LSC_CMASK_XZW] = "xzw",
731 [LSC_CMASK_YZW] = "yzw",
732 [LSC_CMASK_XYZW] = "xyzw",
733 };
734
735 static const char* const lsc_cache_load[] = {
736 [LSC_CACHE_LOAD_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
737 [LSC_CACHE_LOAD_L1UC_L3UC] = "L1UC_L3UC",
738 [LSC_CACHE_LOAD_L1UC_L3C] = "L1UC_L3C",
739 [LSC_CACHE_LOAD_L1C_L3UC] = "L1C_L3UC",
740 [LSC_CACHE_LOAD_L1C_L3C] = "L1C_L3C",
741 [LSC_CACHE_LOAD_L1S_L3UC] = "L1S_L3UC",
742 [LSC_CACHE_LOAD_L1S_L3C] = "L1S_L3C",
743 [LSC_CACHE_LOAD_L1IAR_L3C] = "L1IAR_L3C",
744 };
745
746 static const char* const lsc_cache_store[] = {
747 [LSC_CACHE_STORE_L1STATE_L3MOCS] = "L1STATE_L3MOCS",
748 [LSC_CACHE_STORE_L1UC_L3UC] = "L1UC_L3UC",
749 [LSC_CACHE_STORE_L1UC_L3WB] = "L1UC_L3WB",
750 [LSC_CACHE_STORE_L1WT_L3UC] = "L1WT_L3UC",
751 [LSC_CACHE_STORE_L1WT_L3WB] = "L1WT_L3WB",
752 [LSC_CACHE_STORE_L1S_L3UC] = "L1S_L3UC",
753 [LSC_CACHE_STORE_L1S_L3WB] = "L1S_L3WB",
754 [LSC_CACHE_STORE_L1WB_L3WB] = "L1WB_L3WB",
755 };
756
757 static int column;
758
759 static int
string(FILE * file,const char * string)760 string(FILE *file, const char *string)
761 {
762 fputs(string, file);
763 column += strlen(string);
764 return 0;
765 }
766
767 static int
768 format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
769
770 static int
format(FILE * f,const char * format,...)771 format(FILE *f, const char *format, ...)
772 {
773 char buf[1024];
774 va_list args;
775 va_start(args, format);
776
777 vsnprintf(buf, sizeof(buf) - 1, format, args);
778 va_end(args);
779 string(f, buf);
780 return 0;
781 }
782
783 static int
newline(FILE * f)784 newline(FILE *f)
785 {
786 putc('\n', f);
787 column = 0;
788 return 0;
789 }
790
791 static int
pad(FILE * f,int c)792 pad(FILE *f, int c)
793 {
794 do
795 string(f, " ");
796 while (column < c);
797 return 0;
798 }
799
800 static int
control(FILE * file,const char * name,const char * const ctrl[],unsigned id,int * space)801 control(FILE *file, const char *name, const char *const ctrl[],
802 unsigned id, int *space)
803 {
804 if (!ctrl[id]) {
805 fprintf(file, "*** invalid %s value %d ", name, id);
806 return 1;
807 }
808 if (ctrl[id][0]) {
809 if (space && *space)
810 string(file, " ");
811 string(file, ctrl[id]);
812 if (space)
813 *space = 1;
814 }
815 return 0;
816 }
817
818 static int
print_opcode(FILE * file,const struct brw_isa_info * isa,enum opcode id)819 print_opcode(FILE *file, const struct brw_isa_info *isa,
820 enum opcode id)
821 {
822 const struct opcode_desc *desc = brw_opcode_desc(isa, id);
823 if (!desc) {
824 format(file, "*** invalid opcode value %d ", id);
825 return 1;
826 }
827 string(file, desc->name);
828 return 0;
829 }
830
831 static int
reg(FILE * file,unsigned _reg_file,unsigned _reg_nr)832 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
833 {
834 int err = 0;
835
836 /* Clear the Compr4 instruction compression bit. */
837 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
838 _reg_nr &= ~BRW_MRF_COMPR4;
839
840 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
841 switch (_reg_nr & 0xf0) {
842 case BRW_ARF_NULL:
843 string(file, "null");
844 break;
845 case BRW_ARF_ADDRESS:
846 format(file, "a%d", _reg_nr & 0x0f);
847 break;
848 case BRW_ARF_ACCUMULATOR:
849 format(file, "acc%d", _reg_nr & 0x0f);
850 break;
851 case BRW_ARF_FLAG:
852 format(file, "f%d", _reg_nr & 0x0f);
853 break;
854 case BRW_ARF_MASK:
855 format(file, "mask%d", _reg_nr & 0x0f);
856 break;
857 case BRW_ARF_MASK_STACK:
858 format(file, "ms%d", _reg_nr & 0x0f);
859 break;
860 case BRW_ARF_MASK_STACK_DEPTH:
861 format(file, "msd%d", _reg_nr & 0x0f);
862 break;
863 case BRW_ARF_STATE:
864 format(file, "sr%d", _reg_nr & 0x0f);
865 break;
866 case BRW_ARF_CONTROL:
867 format(file, "cr%d", _reg_nr & 0x0f);
868 break;
869 case BRW_ARF_NOTIFICATION_COUNT:
870 format(file, "n%d", _reg_nr & 0x0f);
871 break;
872 case BRW_ARF_IP:
873 string(file, "ip");
874 return -1;
875 break;
876 case BRW_ARF_TDR:
877 format(file, "tdr0");
878 return -1;
879 case BRW_ARF_TIMESTAMP:
880 format(file, "tm%d", _reg_nr & 0x0f);
881 break;
882 default:
883 format(file, "ARF%d", _reg_nr);
884 break;
885 }
886 } else {
887 err |= control(file, "src reg file", reg_file, _reg_file, NULL);
888 format(file, "%d", _reg_nr);
889 }
890 return err;
891 }
892
893 static int
dest(FILE * file,const struct brw_isa_info * isa,const brw_inst * inst)894 dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
895 {
896 const struct intel_device_info *devinfo = isa->devinfo;
897 enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
898 unsigned elem_size = brw_reg_type_to_size(type);
899 int err = 0;
900
901 if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
902 /* These are fixed for split sends */
903 type = BRW_REGISTER_TYPE_UD;
904 elem_size = 4;
905 if (devinfo->ver >= 12) {
906 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
907 brw_inst_dst_da_reg_nr(devinfo, inst));
908 string(file, brw_reg_type_to_letters(type));
909 } else if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
910 err |= reg(file, brw_inst_send_dst_reg_file(devinfo, inst),
911 brw_inst_dst_da_reg_nr(devinfo, inst));
912 unsigned subreg_nr = brw_inst_dst_da16_subreg_nr(devinfo, inst);
913 if (subreg_nr)
914 format(file, ".%u", subreg_nr);
915 string(file, brw_reg_type_to_letters(type));
916 } else {
917 string(file, "g[a0");
918 if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
919 format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
920 elem_size);
921 if (brw_inst_send_dst_ia16_addr_imm(devinfo, inst))
922 format(file, " %d", brw_inst_send_dst_ia16_addr_imm(devinfo, inst));
923 string(file, "]<");
924 string(file, brw_reg_type_to_letters(type));
925 }
926 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
927 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
928 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
929 brw_inst_dst_da_reg_nr(devinfo, inst));
930 if (err == -1)
931 return 0;
932 if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
933 format(file, ".%"PRIu64, brw_inst_dst_da1_subreg_nr(devinfo, inst) /
934 elem_size);
935 string(file, "<");
936 err |= control(file, "horiz stride", horiz_stride,
937 brw_inst_dst_hstride(devinfo, inst), NULL);
938 string(file, ">");
939 string(file, brw_reg_type_to_letters(type));
940 } else {
941 string(file, "g[a0");
942 if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
943 format(file, ".%"PRIu64, brw_inst_dst_ia_subreg_nr(devinfo, inst) /
944 elem_size);
945 if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
946 format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
947 string(file, "]<");
948 err |= control(file, "horiz stride", horiz_stride,
949 brw_inst_dst_hstride(devinfo, inst), NULL);
950 string(file, ">");
951 string(file, brw_reg_type_to_letters(type));
952 }
953 } else {
954 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
955 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
956 brw_inst_dst_da_reg_nr(devinfo, inst));
957 if (err == -1)
958 return 0;
959 if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
960 format(file, ".%u", 16 / elem_size);
961 string(file, "<1>");
962 err |= control(file, "writemask", writemask,
963 brw_inst_da16_writemask(devinfo, inst), NULL);
964 string(file, brw_reg_type_to_letters(type));
965 } else {
966 err = 1;
967 string(file, "Indirect align16 address mode not supported");
968 }
969 }
970
971 return 0;
972 }
973
974 static int
dest_3src(FILE * file,const struct intel_device_info * devinfo,const brw_inst * inst)975 dest_3src(FILE *file, const struct intel_device_info *devinfo,
976 const brw_inst *inst)
977 {
978 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
979 int err = 0;
980 uint32_t reg_file;
981 unsigned subreg_nr;
982 enum brw_reg_type type;
983
984 if (devinfo->ver < 10 && is_align1)
985 return 0;
986
987 if (devinfo->ver == 6 && brw_inst_3src_a16_dst_reg_file(devinfo, inst))
988 reg_file = BRW_MESSAGE_REGISTER_FILE;
989 else if (devinfo->ver >= 12)
990 reg_file = brw_inst_3src_a1_dst_reg_file(devinfo, inst);
991 else if (is_align1 && brw_inst_3src_a1_dst_reg_file(devinfo, inst))
992 reg_file = BRW_ARCHITECTURE_REGISTER_FILE;
993 else
994 reg_file = BRW_GENERAL_REGISTER_FILE;
995
996 err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
997 if (err == -1)
998 return 0;
999
1000 if (is_align1) {
1001 type = brw_inst_3src_a1_dst_type(devinfo, inst);
1002 subreg_nr = brw_inst_3src_a1_dst_subreg_nr(devinfo, inst);
1003 } else {
1004 type = brw_inst_3src_a16_dst_type(devinfo, inst);
1005 subreg_nr = brw_inst_3src_a16_dst_subreg_nr(devinfo, inst) * 4;
1006 }
1007 subreg_nr /= brw_reg_type_to_size(type);
1008
1009 if (subreg_nr)
1010 format(file, ".%u", subreg_nr);
1011 string(file, "<1>");
1012
1013 if (!is_align1) {
1014 err |= control(file, "writemask", writemask,
1015 brw_inst_3src_a16_dst_writemask(devinfo, inst), NULL);
1016 }
1017 string(file, brw_reg_type_to_letters(type));
1018
1019 return 0;
1020 }
1021
1022 static int
src_align1_region(FILE * file,unsigned _vert_stride,unsigned _width,unsigned _horiz_stride)1023 src_align1_region(FILE *file,
1024 unsigned _vert_stride, unsigned _width,
1025 unsigned _horiz_stride)
1026 {
1027 int err = 0;
1028 string(file, "<");
1029 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
1030 string(file, ",");
1031 err |= control(file, "width", width, _width, NULL);
1032 string(file, ",");
1033 err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
1034 string(file, ">");
1035 return err;
1036 }
1037
1038 static int
src_da1(FILE * file,const struct intel_device_info * devinfo,unsigned opcode,enum brw_reg_type type,unsigned _reg_file,unsigned _vert_stride,unsigned _width,unsigned _horiz_stride,unsigned reg_num,unsigned sub_reg_num,unsigned __abs,unsigned _negate)1039 src_da1(FILE *file,
1040 const struct intel_device_info *devinfo,
1041 unsigned opcode,
1042 enum brw_reg_type type, unsigned _reg_file,
1043 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
1044 unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
1045 unsigned _negate)
1046 {
1047 int err = 0;
1048
1049 if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1050 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1051 else
1052 err |= control(file, "negate", m_negate, _negate, NULL);
1053
1054 err |= control(file, "abs", _abs, __abs, NULL);
1055
1056 err |= reg(file, _reg_file, reg_num);
1057 if (err == -1)
1058 return 0;
1059 if (sub_reg_num) {
1060 unsigned elem_size = brw_reg_type_to_size(type);
1061 format(file, ".%d", sub_reg_num / elem_size); /* use formal style like spec */
1062 }
1063 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1064 string(file, brw_reg_type_to_letters(type));
1065 return err;
1066 }
1067
1068 static int
src_ia1(FILE * file,const struct intel_device_info * devinfo,unsigned opcode,enum brw_reg_type type,int _addr_imm,unsigned _addr_subreg_nr,unsigned _negate,unsigned __abs,unsigned _horiz_stride,unsigned _width,unsigned _vert_stride)1069 src_ia1(FILE *file,
1070 const struct intel_device_info *devinfo,
1071 unsigned opcode,
1072 enum brw_reg_type type,
1073 int _addr_imm,
1074 unsigned _addr_subreg_nr,
1075 unsigned _negate,
1076 unsigned __abs,
1077 unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
1078 {
1079 int err = 0;
1080
1081 if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1082 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1083 else
1084 err |= control(file, "negate", m_negate, _negate, NULL);
1085
1086 err |= control(file, "abs", _abs, __abs, NULL);
1087
1088 string(file, "g[a0");
1089 if (_addr_subreg_nr)
1090 format(file, ".%d", _addr_subreg_nr);
1091 if (_addr_imm)
1092 format(file, " %d", _addr_imm);
1093 string(file, "]");
1094 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1095 string(file, brw_reg_type_to_letters(type));
1096 return err;
1097 }
1098
1099 static int
src_swizzle(FILE * file,unsigned swiz)1100 src_swizzle(FILE *file, unsigned swiz)
1101 {
1102 unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
1103 unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
1104 unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
1105 unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
1106 int err = 0;
1107
1108 if (x == y && x == z && x == w) {
1109 string(file, ".");
1110 err |= control(file, "channel select", chan_sel, x, NULL);
1111 } else if (swiz != BRW_SWIZZLE_XYZW) {
1112 string(file, ".");
1113 err |= control(file, "channel select", chan_sel, x, NULL);
1114 err |= control(file, "channel select", chan_sel, y, NULL);
1115 err |= control(file, "channel select", chan_sel, z, NULL);
1116 err |= control(file, "channel select", chan_sel, w, NULL);
1117 }
1118 return err;
1119 }
1120
1121 static int
src_da16(FILE * file,const struct intel_device_info * devinfo,unsigned opcode,enum brw_reg_type type,unsigned _reg_file,unsigned _vert_stride,unsigned _reg_nr,unsigned _subreg_nr,unsigned __abs,unsigned _negate,unsigned swz_x,unsigned swz_y,unsigned swz_z,unsigned swz_w)1122 src_da16(FILE *file,
1123 const struct intel_device_info *devinfo,
1124 unsigned opcode,
1125 enum brw_reg_type type,
1126 unsigned _reg_file,
1127 unsigned _vert_stride,
1128 unsigned _reg_nr,
1129 unsigned _subreg_nr,
1130 unsigned __abs,
1131 unsigned _negate,
1132 unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
1133 {
1134 int err = 0;
1135
1136 if (devinfo->ver >= 8 && is_logic_instruction(opcode))
1137 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
1138 else
1139 err |= control(file, "negate", m_negate, _negate, NULL);
1140
1141 err |= control(file, "abs", _abs, __abs, NULL);
1142
1143 err |= reg(file, _reg_file, _reg_nr);
1144 if (err == -1)
1145 return 0;
1146 if (_subreg_nr) {
1147 unsigned elem_size = brw_reg_type_to_size(type);
1148
1149 /* bit4 for subreg number byte addressing. Make this same meaning as
1150 in da1 case, so output looks consistent. */
1151 format(file, ".%d", 16 / elem_size);
1152 }
1153 string(file, "<");
1154 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
1155 string(file, ">");
1156 err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
1157 string(file, brw_reg_type_to_letters(type));
1158 return err;
1159 }
1160
1161 static enum brw_vertical_stride
vstride_from_align1_3src_vstride(const struct intel_device_info * devinfo,enum gfx10_align1_3src_vertical_stride vstride)1162 vstride_from_align1_3src_vstride(const struct intel_device_info *devinfo,
1163 enum gfx10_align1_3src_vertical_stride vstride)
1164 {
1165 switch (vstride) {
1166 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1167 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_2:
1168 if (devinfo->ver >= 12)
1169 return BRW_VERTICAL_STRIDE_1;
1170 else
1171 return BRW_VERTICAL_STRIDE_2;
1172 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1173 case BRW_ALIGN1_3SRC_VERTICAL_STRIDE_8: return BRW_VERTICAL_STRIDE_8;
1174 default:
1175 unreachable("not reached");
1176 }
1177 }
1178
1179 static enum brw_horizontal_stride
hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)1180 hstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
1181 {
1182 switch (hstride) {
1183 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_HORIZONTAL_STRIDE_0;
1184 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_HORIZONTAL_STRIDE_1;
1185 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_HORIZONTAL_STRIDE_2;
1186 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_HORIZONTAL_STRIDE_4;
1187 default:
1188 unreachable("not reached");
1189 }
1190 }
1191
1192 static enum brw_vertical_stride
vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)1193 vstride_from_align1_3src_hstride(enum gfx10_align1_3src_src_horizontal_stride hstride)
1194 {
1195 switch (hstride) {
1196 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0: return BRW_VERTICAL_STRIDE_0;
1197 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1: return BRW_VERTICAL_STRIDE_1;
1198 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2;
1199 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4: return BRW_VERTICAL_STRIDE_4;
1200 default:
1201 unreachable("not reached");
1202 }
1203 }
1204
1205 /* From "GFX10 Regioning Rules for Align1 Ternary Operations" in the
1206 * "Register Region Restrictions" documentation
1207 */
1208 static enum brw_width
implied_width(enum brw_vertical_stride _vert_stride,enum brw_horizontal_stride _horiz_stride)1209 implied_width(enum brw_vertical_stride _vert_stride,
1210 enum brw_horizontal_stride _horiz_stride)
1211 {
1212 /* "1. Width is 1 when Vertical and Horizontal Strides are both zero." */
1213 if (_vert_stride == BRW_VERTICAL_STRIDE_0 &&
1214 _horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1215 return BRW_WIDTH_1;
1216
1217 /* "2. Width is equal to vertical stride when Horizontal Stride is zero." */
1218 } else if (_horiz_stride == BRW_HORIZONTAL_STRIDE_0) {
1219 switch (_vert_stride) {
1220 case BRW_VERTICAL_STRIDE_1: return BRW_WIDTH_1;
1221 case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2;
1222 case BRW_VERTICAL_STRIDE_4: return BRW_WIDTH_4;
1223 case BRW_VERTICAL_STRIDE_8: return BRW_WIDTH_8;
1224 case BRW_VERTICAL_STRIDE_0:
1225 default:
1226 unreachable("not reached");
1227 }
1228
1229 } else {
1230 /* FINISHME: Implement these: */
1231
1232 /* "3. Width is equal to Vertical Stride/Horizontal Stride when both
1233 * Strides are non-zero.
1234 *
1235 * 4. Vertical Stride must not be zero if Horizontal Stride is non-zero.
1236 * This implies Vertical Stride is always greater than Horizontal
1237 * Stride."
1238 *
1239 * Given these statements and the knowledge that the stride and width
1240 * values are encoded in logarithmic form, we can perform the division
1241 * by just subtracting.
1242 */
1243 return _vert_stride - _horiz_stride;
1244 }
1245 }
1246
1247 static int
src0_3src(FILE * file,const struct intel_device_info * devinfo,const brw_inst * inst)1248 src0_3src(FILE *file, const struct intel_device_info *devinfo,
1249 const brw_inst *inst)
1250 {
1251 int err = 0;
1252 unsigned reg_nr, subreg_nr;
1253 enum brw_reg_file _file;
1254 enum brw_reg_type type;
1255 enum brw_vertical_stride _vert_stride;
1256 enum brw_width _width;
1257 enum brw_horizontal_stride _horiz_stride;
1258 bool is_scalar_region;
1259 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1260
1261 if (devinfo->ver < 10 && is_align1)
1262 return 0;
1263
1264 if (is_align1) {
1265 if (devinfo->ver >= 12 && !brw_inst_3src_a1_src0_is_imm(devinfo, inst)) {
1266 _file = brw_inst_3src_a1_src0_reg_file(devinfo, inst);
1267 } else if (brw_inst_3src_a1_src0_reg_file(devinfo, inst) ==
1268 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1269 _file = BRW_GENERAL_REGISTER_FILE;
1270 } else if (brw_inst_3src_a1_src0_type(devinfo, inst) ==
1271 BRW_REGISTER_TYPE_NF) {
1272 _file = BRW_ARCHITECTURE_REGISTER_FILE;
1273 } else {
1274 _file = BRW_IMMEDIATE_VALUE;
1275 uint16_t imm_val = brw_inst_3src_a1_src0_imm(devinfo, inst);
1276 enum brw_reg_type type = brw_inst_3src_a1_src0_type(devinfo, inst);
1277
1278 if (type == BRW_REGISTER_TYPE_W) {
1279 format(file, "%dW", imm_val);
1280 } else if (type == BRW_REGISTER_TYPE_UW) {
1281 format(file, "0x%04xUW", imm_val);
1282 } else if (type == BRW_REGISTER_TYPE_HF) {
1283 format(file, "0x%04xHF", imm_val);
1284 }
1285 return 0;
1286 }
1287
1288 reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1289 subreg_nr = brw_inst_3src_a1_src0_subreg_nr(devinfo, inst);
1290 type = brw_inst_3src_a1_src0_type(devinfo, inst);
1291 _vert_stride = vstride_from_align1_3src_vstride(
1292 devinfo, brw_inst_3src_a1_src0_vstride(devinfo, inst));
1293 _horiz_stride = hstride_from_align1_3src_hstride(
1294 brw_inst_3src_a1_src0_hstride(devinfo, inst));
1295 _width = implied_width(_vert_stride, _horiz_stride);
1296 } else {
1297 _file = BRW_GENERAL_REGISTER_FILE;
1298 reg_nr = brw_inst_3src_src0_reg_nr(devinfo, inst);
1299 subreg_nr = brw_inst_3src_a16_src0_subreg_nr(devinfo, inst) * 4;
1300 type = brw_inst_3src_a16_src_type(devinfo, inst);
1301
1302 if (brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst)) {
1303 _vert_stride = BRW_VERTICAL_STRIDE_0;
1304 _width = BRW_WIDTH_1;
1305 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1306 } else {
1307 _vert_stride = BRW_VERTICAL_STRIDE_4;
1308 _width = BRW_WIDTH_4;
1309 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1310 }
1311 }
1312 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1313 _width == BRW_WIDTH_1 &&
1314 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1315
1316 subreg_nr /= brw_reg_type_to_size(type);
1317
1318 err |= control(file, "negate", m_negate,
1319 brw_inst_3src_src0_negate(devinfo, inst), NULL);
1320 err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL);
1321
1322 err |= reg(file, _file, reg_nr);
1323 if (err == -1)
1324 return 0;
1325 if (subreg_nr || is_scalar_region)
1326 format(file, ".%d", subreg_nr);
1327 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1328 if (!is_scalar_region && !is_align1)
1329 err |= src_swizzle(file, brw_inst_3src_a16_src0_swizzle(devinfo, inst));
1330 string(file, brw_reg_type_to_letters(type));
1331 return err;
1332 }
1333
1334 static int
src1_3src(FILE * file,const struct intel_device_info * devinfo,const brw_inst * inst)1335 src1_3src(FILE *file, const struct intel_device_info *devinfo,
1336 const brw_inst *inst)
1337 {
1338 int err = 0;
1339 unsigned reg_nr, subreg_nr;
1340 enum brw_reg_file _file;
1341 enum brw_reg_type type;
1342 enum brw_vertical_stride _vert_stride;
1343 enum brw_width _width;
1344 enum brw_horizontal_stride _horiz_stride;
1345 bool is_scalar_region;
1346 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1347
1348 if (devinfo->ver < 10 && is_align1)
1349 return 0;
1350
1351 if (is_align1) {
1352 if (devinfo->ver >= 12) {
1353 _file = brw_inst_3src_a1_src1_reg_file(devinfo, inst);
1354 } else if (brw_inst_3src_a1_src1_reg_file(devinfo, inst) ==
1355 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1356 _file = BRW_GENERAL_REGISTER_FILE;
1357 } else {
1358 _file = BRW_ARCHITECTURE_REGISTER_FILE;
1359 }
1360
1361 reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1362 subreg_nr = brw_inst_3src_a1_src1_subreg_nr(devinfo, inst);
1363 type = brw_inst_3src_a1_src1_type(devinfo, inst);
1364
1365 _vert_stride = vstride_from_align1_3src_vstride(
1366 devinfo, brw_inst_3src_a1_src1_vstride(devinfo, inst));
1367 _horiz_stride = hstride_from_align1_3src_hstride(
1368 brw_inst_3src_a1_src1_hstride(devinfo, inst));
1369 _width = implied_width(_vert_stride, _horiz_stride);
1370 } else {
1371 _file = BRW_GENERAL_REGISTER_FILE;
1372 reg_nr = brw_inst_3src_src1_reg_nr(devinfo, inst);
1373 subreg_nr = brw_inst_3src_a16_src1_subreg_nr(devinfo, inst) * 4;
1374 type = brw_inst_3src_a16_src_type(devinfo, inst);
1375
1376 if (brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst)) {
1377 _vert_stride = BRW_VERTICAL_STRIDE_0;
1378 _width = BRW_WIDTH_1;
1379 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1380 } else {
1381 _vert_stride = BRW_VERTICAL_STRIDE_4;
1382 _width = BRW_WIDTH_4;
1383 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1384 }
1385 }
1386 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1387 _width == BRW_WIDTH_1 &&
1388 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1389
1390 subreg_nr /= brw_reg_type_to_size(type);
1391
1392 err |= control(file, "negate", m_negate,
1393 brw_inst_3src_src1_negate(devinfo, inst), NULL);
1394 err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL);
1395
1396 err |= reg(file, _file, reg_nr);
1397 if (err == -1)
1398 return 0;
1399 if (subreg_nr || is_scalar_region)
1400 format(file, ".%d", subreg_nr);
1401 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1402 if (!is_scalar_region && !is_align1)
1403 err |= src_swizzle(file, brw_inst_3src_a16_src1_swizzle(devinfo, inst));
1404 string(file, brw_reg_type_to_letters(type));
1405 return err;
1406 }
1407
1408 static int
src2_3src(FILE * file,const struct intel_device_info * devinfo,const brw_inst * inst)1409 src2_3src(FILE *file, const struct intel_device_info *devinfo,
1410 const brw_inst *inst)
1411 {
1412 int err = 0;
1413 unsigned reg_nr, subreg_nr;
1414 enum brw_reg_file _file;
1415 enum brw_reg_type type;
1416 enum brw_vertical_stride _vert_stride;
1417 enum brw_width _width;
1418 enum brw_horizontal_stride _horiz_stride;
1419 bool is_scalar_region;
1420 bool is_align1 = brw_inst_3src_access_mode(devinfo, inst) == BRW_ALIGN_1;
1421
1422 if (devinfo->ver < 10 && is_align1)
1423 return 0;
1424
1425 if (is_align1) {
1426 if (devinfo->ver >= 12 && !brw_inst_3src_a1_src2_is_imm(devinfo, inst)) {
1427 _file = brw_inst_3src_a1_src2_reg_file(devinfo, inst);
1428 } else if (brw_inst_3src_a1_src2_reg_file(devinfo, inst) ==
1429 BRW_ALIGN1_3SRC_GENERAL_REGISTER_FILE) {
1430 _file = BRW_GENERAL_REGISTER_FILE;
1431 } else {
1432 _file = BRW_IMMEDIATE_VALUE;
1433 uint16_t imm_val = brw_inst_3src_a1_src2_imm(devinfo, inst);
1434 enum brw_reg_type type = brw_inst_3src_a1_src2_type(devinfo, inst);
1435
1436 if (type == BRW_REGISTER_TYPE_W) {
1437 format(file, "%dW", imm_val);
1438 } else if (type == BRW_REGISTER_TYPE_UW) {
1439 format(file, "0x%04xUW", imm_val);
1440 } else if (type == BRW_REGISTER_TYPE_HF) {
1441 format(file, "0x%04xHF", imm_val);
1442 }
1443 return 0;
1444 }
1445
1446 reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1447 subreg_nr = brw_inst_3src_a1_src2_subreg_nr(devinfo, inst);
1448 type = brw_inst_3src_a1_src2_type(devinfo, inst);
1449 /* FINISHME: No vertical stride on src2. Is using the hstride in place
1450 * correct? Doesn't seem like it, since there's hstride=1 but
1451 * no vstride=1.
1452 */
1453 _vert_stride = vstride_from_align1_3src_hstride(
1454 brw_inst_3src_a1_src2_hstride(devinfo, inst));
1455 _horiz_stride = hstride_from_align1_3src_hstride(
1456 brw_inst_3src_a1_src2_hstride(devinfo, inst));
1457 _width = implied_width(_vert_stride, _horiz_stride);
1458 } else {
1459 _file = BRW_GENERAL_REGISTER_FILE;
1460 reg_nr = brw_inst_3src_src2_reg_nr(devinfo, inst);
1461 subreg_nr = brw_inst_3src_a16_src2_subreg_nr(devinfo, inst) * 4;
1462 type = brw_inst_3src_a16_src_type(devinfo, inst);
1463
1464 if (brw_inst_3src_a16_src2_rep_ctrl(devinfo, inst)) {
1465 _vert_stride = BRW_VERTICAL_STRIDE_0;
1466 _width = BRW_WIDTH_1;
1467 _horiz_stride = BRW_HORIZONTAL_STRIDE_0;
1468 } else {
1469 _vert_stride = BRW_VERTICAL_STRIDE_4;
1470 _width = BRW_WIDTH_4;
1471 _horiz_stride = BRW_HORIZONTAL_STRIDE_1;
1472 }
1473 }
1474 is_scalar_region = _vert_stride == BRW_VERTICAL_STRIDE_0 &&
1475 _width == BRW_WIDTH_1 &&
1476 _horiz_stride == BRW_HORIZONTAL_STRIDE_0;
1477
1478 subreg_nr /= brw_reg_type_to_size(type);
1479
1480 err |= control(file, "negate", m_negate,
1481 brw_inst_3src_src2_negate(devinfo, inst), NULL);
1482 err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL);
1483
1484 err |= reg(file, _file, reg_nr);
1485 if (err == -1)
1486 return 0;
1487 if (subreg_nr || is_scalar_region)
1488 format(file, ".%d", subreg_nr);
1489 src_align1_region(file, _vert_stride, _width, _horiz_stride);
1490 if (!is_scalar_region && !is_align1)
1491 err |= src_swizzle(file, brw_inst_3src_a16_src2_swizzle(devinfo, inst));
1492 string(file, brw_reg_type_to_letters(type));
1493 return err;
1494 }
1495
1496 static int
imm(FILE * file,const struct brw_isa_info * isa,enum brw_reg_type type,const brw_inst * inst)1497 imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
1498 const brw_inst *inst)
1499 {
1500 const struct intel_device_info *devinfo = isa->devinfo;
1501
1502 switch (type) {
1503 case BRW_REGISTER_TYPE_UQ:
1504 format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
1505 break;
1506 case BRW_REGISTER_TYPE_Q:
1507 format(file, "0x%016"PRIx64"Q", brw_inst_imm_uq(devinfo, inst));
1508 break;
1509 case BRW_REGISTER_TYPE_UD:
1510 format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
1511 break;
1512 case BRW_REGISTER_TYPE_D:
1513 format(file, "%dD", brw_inst_imm_d(devinfo, inst));
1514 break;
1515 case BRW_REGISTER_TYPE_UW:
1516 format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
1517 break;
1518 case BRW_REGISTER_TYPE_W:
1519 format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
1520 break;
1521 case BRW_REGISTER_TYPE_UV:
1522 format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
1523 break;
1524 case BRW_REGISTER_TYPE_VF:
1525 format(file, "0x%"PRIx64"VF", brw_inst_bits(inst, 127, 96));
1526 pad(file, 48);
1527 format(file, "/* [%-gF, %-gF, %-gF, %-gF]VF */",
1528 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
1529 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
1530 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
1531 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
1532 break;
1533 case BRW_REGISTER_TYPE_V:
1534 format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
1535 break;
1536 case BRW_REGISTER_TYPE_F:
1537 /* The DIM instruction's src0 uses an F type but contains a
1538 * 64-bit immediate
1539 */
1540 if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DIM) {
1541 format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64));
1542 pad(file, 48);
1543 format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst));
1544 } else {
1545 format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 96));
1546 pad(file, 48);
1547 format(file, " /* %-gF */", brw_inst_imm_f(devinfo, inst));
1548 }
1549 break;
1550 case BRW_REGISTER_TYPE_DF:
1551 format(file, "0x%016"PRIx64"DF", brw_inst_bits(inst, 127, 64));
1552 pad(file, 48);
1553 format(file, "/* %-gDF */", brw_inst_imm_df(devinfo, inst));
1554 break;
1555 case BRW_REGISTER_TYPE_HF:
1556 string(file, "Half Float IMM");
1557 break;
1558 case BRW_REGISTER_TYPE_NF:
1559 case BRW_REGISTER_TYPE_UB:
1560 case BRW_REGISTER_TYPE_B:
1561 format(file, "*** invalid immediate type %d ", type);
1562 }
1563 return 0;
1564 }
1565
1566 static int
src_sends_da(FILE * file,const struct intel_device_info * devinfo,enum brw_reg_type type,enum brw_reg_file _reg_file,unsigned _reg_nr,unsigned _reg_subnr)1567 src_sends_da(FILE *file,
1568 const struct intel_device_info *devinfo,
1569 enum brw_reg_type type,
1570 enum brw_reg_file _reg_file,
1571 unsigned _reg_nr,
1572 unsigned _reg_subnr)
1573 {
1574 int err = 0;
1575
1576 err |= reg(file, _reg_file, _reg_nr);
1577 if (err == -1)
1578 return 0;
1579 if (_reg_subnr)
1580 format(file, ".1");
1581 string(file, brw_reg_type_to_letters(type));
1582
1583 return err;
1584 }
1585
1586 static int
src_sends_ia(FILE * file,const struct intel_device_info * devinfo,enum brw_reg_type type,int _addr_imm,unsigned _addr_subreg_nr)1587 src_sends_ia(FILE *file,
1588 const struct intel_device_info *devinfo,
1589 enum brw_reg_type type,
1590 int _addr_imm,
1591 unsigned _addr_subreg_nr)
1592 {
1593 string(file, "g[a0");
1594 if (_addr_subreg_nr)
1595 format(file, ".1");
1596 if (_addr_imm)
1597 format(file, " %d", _addr_imm);
1598 string(file, "]");
1599 string(file, brw_reg_type_to_letters(type));
1600
1601 return 0;
1602 }
1603
1604 static int
src_send_desc_ia(FILE * file,const struct intel_device_info * devinfo,unsigned _addr_subreg_nr)1605 src_send_desc_ia(FILE *file,
1606 const struct intel_device_info *devinfo,
1607 unsigned _addr_subreg_nr)
1608 {
1609 string(file, "a0");
1610 if (_addr_subreg_nr)
1611 format(file, ".%d", _addr_subreg_nr);
1612 format(file, "<0>UD");
1613
1614 return 0;
1615 }
1616
1617 static int
src0(FILE * file,const struct brw_isa_info * isa,const brw_inst * inst)1618 src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
1619 {
1620 const struct intel_device_info *devinfo = isa->devinfo;
1621
1622 if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
1623 if (devinfo->ver >= 12) {
1624 return src_sends_da(file,
1625 devinfo,
1626 BRW_REGISTER_TYPE_UD,
1627 brw_inst_send_src0_reg_file(devinfo, inst),
1628 brw_inst_src0_da_reg_nr(devinfo, inst),
1629 0);
1630 } else if (brw_inst_send_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1631 return src_sends_da(file,
1632 devinfo,
1633 BRW_REGISTER_TYPE_UD,
1634 BRW_GENERAL_REGISTER_FILE,
1635 brw_inst_src0_da_reg_nr(devinfo, inst),
1636 brw_inst_src0_da16_subreg_nr(devinfo, inst));
1637 } else {
1638 return src_sends_ia(file,
1639 devinfo,
1640 BRW_REGISTER_TYPE_UD,
1641 brw_inst_send_src0_ia16_addr_imm(devinfo, inst),
1642 brw_inst_src0_ia_subreg_nr(devinfo, inst));
1643 }
1644 } else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1645 return imm(file, isa, brw_inst_src0_type(devinfo, inst), inst);
1646 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1647 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1648 return src_da1(file,
1649 devinfo,
1650 brw_inst_opcode(isa, inst),
1651 brw_inst_src0_type(devinfo, inst),
1652 brw_inst_src0_reg_file(devinfo, inst),
1653 brw_inst_src0_vstride(devinfo, inst),
1654 brw_inst_src0_width(devinfo, inst),
1655 brw_inst_src0_hstride(devinfo, inst),
1656 brw_inst_src0_da_reg_nr(devinfo, inst),
1657 brw_inst_src0_da1_subreg_nr(devinfo, inst),
1658 brw_inst_src0_abs(devinfo, inst),
1659 brw_inst_src0_negate(devinfo, inst));
1660 } else {
1661 return src_ia1(file,
1662 devinfo,
1663 brw_inst_opcode(isa, inst),
1664 brw_inst_src0_type(devinfo, inst),
1665 brw_inst_src0_ia1_addr_imm(devinfo, inst),
1666 brw_inst_src0_ia_subreg_nr(devinfo, inst),
1667 brw_inst_src0_negate(devinfo, inst),
1668 brw_inst_src0_abs(devinfo, inst),
1669 brw_inst_src0_hstride(devinfo, inst),
1670 brw_inst_src0_width(devinfo, inst),
1671 brw_inst_src0_vstride(devinfo, inst));
1672 }
1673 } else {
1674 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1675 return src_da16(file,
1676 devinfo,
1677 brw_inst_opcode(isa, inst),
1678 brw_inst_src0_type(devinfo, inst),
1679 brw_inst_src0_reg_file(devinfo, inst),
1680 brw_inst_src0_vstride(devinfo, inst),
1681 brw_inst_src0_da_reg_nr(devinfo, inst),
1682 brw_inst_src0_da16_subreg_nr(devinfo, inst),
1683 brw_inst_src0_abs(devinfo, inst),
1684 brw_inst_src0_negate(devinfo, inst),
1685 brw_inst_src0_da16_swiz_x(devinfo, inst),
1686 brw_inst_src0_da16_swiz_y(devinfo, inst),
1687 brw_inst_src0_da16_swiz_z(devinfo, inst),
1688 brw_inst_src0_da16_swiz_w(devinfo, inst));
1689 } else {
1690 string(file, "Indirect align16 address mode not supported");
1691 return 1;
1692 }
1693 }
1694 }
1695
1696 static int
src1(FILE * file,const struct brw_isa_info * isa,const brw_inst * inst)1697 src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
1698 {
1699 const struct intel_device_info *devinfo = isa->devinfo;
1700
1701 if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
1702 return src_sends_da(file,
1703 devinfo,
1704 BRW_REGISTER_TYPE_UD,
1705 brw_inst_send_src1_reg_file(devinfo, inst),
1706 brw_inst_send_src1_reg_nr(devinfo, inst),
1707 0 /* subreg_nr */);
1708 } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1709 return imm(file, isa, brw_inst_src1_type(devinfo, inst), inst);
1710 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1711 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1712 return src_da1(file,
1713 devinfo,
1714 brw_inst_opcode(isa, inst),
1715 brw_inst_src1_type(devinfo, inst),
1716 brw_inst_src1_reg_file(devinfo, inst),
1717 brw_inst_src1_vstride(devinfo, inst),
1718 brw_inst_src1_width(devinfo, inst),
1719 brw_inst_src1_hstride(devinfo, inst),
1720 brw_inst_src1_da_reg_nr(devinfo, inst),
1721 brw_inst_src1_da1_subreg_nr(devinfo, inst),
1722 brw_inst_src1_abs(devinfo, inst),
1723 brw_inst_src1_negate(devinfo, inst));
1724 } else {
1725 return src_ia1(file,
1726 devinfo,
1727 brw_inst_opcode(isa, inst),
1728 brw_inst_src1_type(devinfo, inst),
1729 brw_inst_src1_ia1_addr_imm(devinfo, inst),
1730 brw_inst_src1_ia_subreg_nr(devinfo, inst),
1731 brw_inst_src1_negate(devinfo, inst),
1732 brw_inst_src1_abs(devinfo, inst),
1733 brw_inst_src1_hstride(devinfo, inst),
1734 brw_inst_src1_width(devinfo, inst),
1735 brw_inst_src1_vstride(devinfo, inst));
1736 }
1737 } else {
1738 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1739 return src_da16(file,
1740 devinfo,
1741 brw_inst_opcode(isa, inst),
1742 brw_inst_src1_type(devinfo, inst),
1743 brw_inst_src1_reg_file(devinfo, inst),
1744 brw_inst_src1_vstride(devinfo, inst),
1745 brw_inst_src1_da_reg_nr(devinfo, inst),
1746 brw_inst_src1_da16_subreg_nr(devinfo, inst),
1747 brw_inst_src1_abs(devinfo, inst),
1748 brw_inst_src1_negate(devinfo, inst),
1749 brw_inst_src1_da16_swiz_x(devinfo, inst),
1750 brw_inst_src1_da16_swiz_y(devinfo, inst),
1751 brw_inst_src1_da16_swiz_z(devinfo, inst),
1752 brw_inst_src1_da16_swiz_w(devinfo, inst));
1753 } else {
1754 string(file, "Indirect align16 address mode not supported");
1755 return 1;
1756 }
1757 }
1758 }
1759
1760 static int
qtr_ctrl(FILE * file,const struct intel_device_info * devinfo,const brw_inst * inst)1761 qtr_ctrl(FILE *file, const struct intel_device_info *devinfo,
1762 const brw_inst *inst)
1763 {
1764 int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
1765 int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
1766 const unsigned nib_ctl = devinfo->ver < 7 ? 0 :
1767 brw_inst_nib_control(devinfo, inst);
1768
1769 if (exec_size < 8 || nib_ctl) {
1770 format(file, " %dN", qtr_ctl * 2 + nib_ctl + 1);
1771 } else if (exec_size == 8) {
1772 switch (qtr_ctl) {
1773 case 0:
1774 string(file, " 1Q");
1775 break;
1776 case 1:
1777 string(file, " 2Q");
1778 break;
1779 case 2:
1780 string(file, " 3Q");
1781 break;
1782 case 3:
1783 string(file, " 4Q");
1784 break;
1785 }
1786 } else if (exec_size == 16) {
1787 if (qtr_ctl < 2)
1788 string(file, " 1H");
1789 else
1790 string(file, " 2H");
1791 }
1792 return 0;
1793 }
1794
1795 static int
swsb(FILE * file,const struct brw_isa_info * isa,const brw_inst * inst)1796 swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
1797 {
1798 const struct intel_device_info *devinfo = isa->devinfo;
1799 const enum opcode opcode = brw_inst_opcode(isa, inst);
1800 const uint8_t x = brw_inst_swsb(devinfo, inst);
1801 const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, opcode, x);
1802 if (swsb.regdist)
1803 format(file, " %s@%d",
1804 (swsb.pipe == TGL_PIPE_FLOAT ? "F" :
1805 swsb.pipe == TGL_PIPE_INT ? "I" :
1806 swsb.pipe == TGL_PIPE_LONG ? "L" :
1807 swsb.pipe == TGL_PIPE_ALL ? "A" : "" ),
1808 swsb.regdist);
1809 if (swsb.mode)
1810 format(file, " $%d%s", swsb.sbid,
1811 (swsb.mode & TGL_SBID_SET ? "" :
1812 swsb.mode & TGL_SBID_DST ? ".dst" : ".src"));
1813 return 0;
1814 }
1815
1816 #ifdef DEBUG
1817 static __attribute__((__unused__)) int
brw_disassemble_imm(const struct brw_isa_info * isa,uint32_t dw3,uint32_t dw2,uint32_t dw1,uint32_t dw0)1818 brw_disassemble_imm(const struct brw_isa_info *isa,
1819 uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
1820 {
1821 brw_inst inst;
1822 inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0);
1823 inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2);
1824 return brw_disassemble_inst(stderr, isa, &inst, false, 0, NULL);
1825 }
1826 #endif
1827
1828 static void
write_label(FILE * file,const struct intel_device_info * devinfo,const struct brw_label * root_label,int offset,int jump)1829 write_label(FILE *file, const struct intel_device_info *devinfo,
1830 const struct brw_label *root_label,
1831 int offset, int jump)
1832 {
1833 if (root_label != NULL) {
1834 int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo);
1835 const struct brw_label *label =
1836 brw_find_label(root_label, offset + jump * to_bytes_scale);
1837 if (label != NULL) {
1838 format(file, " LABEL%d", label->number);
1839 }
1840 }
1841 }
1842
1843 static void
lsc_disassemble_ex_desc(const struct intel_device_info * devinfo,uint32_t imm_desc,uint32_t imm_ex_desc,FILE * file)1844 lsc_disassemble_ex_desc(const struct intel_device_info *devinfo,
1845 uint32_t imm_desc,
1846 uint32_t imm_ex_desc,
1847 FILE *file)
1848 {
1849 const unsigned addr_type = lsc_msg_desc_addr_type(devinfo, imm_desc);
1850 switch (addr_type) {
1851 case LSC_ADDR_SURFTYPE_FLAT:
1852 format(file, "base_offset %u ",
1853 lsc_flat_ex_desc_base_offset(devinfo, imm_ex_desc));
1854 break;
1855 case LSC_ADDR_SURFTYPE_BSS:
1856 case LSC_ADDR_SURFTYPE_SS:
1857 format(file, "surface_state_index %u ",
1858 lsc_bss_ex_desc_index(devinfo, imm_ex_desc));
1859 break;
1860 case LSC_ADDR_SURFTYPE_BTI:
1861 format(file, "BTI %u ",
1862 lsc_bti_ex_desc_index(devinfo, imm_ex_desc));
1863 format(file, "base_offset %u ",
1864 lsc_bti_ex_desc_base_offset(devinfo, imm_ex_desc));
1865 break;
1866 default:
1867 format(file, "unsupported address surface type %d", addr_type);
1868 break;
1869 }
1870 }
1871
1872 static inline bool
brw_sfid_is_lsc(unsigned sfid)1873 brw_sfid_is_lsc(unsigned sfid)
1874 {
1875 switch (sfid) {
1876 case GFX12_SFID_UGM:
1877 case GFX12_SFID_SLM:
1878 case GFX12_SFID_TGM:
1879 return true;
1880 default:
1881 break;
1882 }
1883
1884 return false;
1885 }
1886
1887 int
brw_disassemble_inst(FILE * file,const struct brw_isa_info * isa,const brw_inst * inst,bool is_compacted,int offset,const struct brw_label * root_label)1888 brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
1889 const brw_inst *inst, bool is_compacted,
1890 int offset, const struct brw_label *root_label)
1891 {
1892 const struct intel_device_info *devinfo = isa->devinfo;
1893
1894 int err = 0;
1895 int space = 0;
1896
1897 const enum opcode opcode = brw_inst_opcode(isa, inst);
1898 const struct opcode_desc *desc = brw_opcode_desc(isa, opcode);
1899
1900 if (brw_inst_pred_control(devinfo, inst)) {
1901 string(file, "(");
1902 err |= control(file, "predicate inverse", pred_inv,
1903 brw_inst_pred_inv(devinfo, inst), NULL);
1904 format(file, "f%"PRIu64".%"PRIu64,
1905 devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1906 brw_inst_flag_subreg_nr(devinfo, inst));
1907 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1908 err |= control(file, "predicate control align1", pred_ctrl_align1,
1909 brw_inst_pred_control(devinfo, inst), NULL);
1910 } else {
1911 err |= control(file, "predicate control align16", pred_ctrl_align16,
1912 brw_inst_pred_control(devinfo, inst), NULL);
1913 }
1914 string(file, ") ");
1915 }
1916
1917 err |= print_opcode(file, isa, opcode);
1918
1919 if (!is_send(opcode))
1920 err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
1921 NULL);
1922
1923 err |= control(file, "debug control", debug_ctrl,
1924 brw_inst_debug_control(devinfo, inst), NULL);
1925
1926 if (opcode == BRW_OPCODE_MATH) {
1927 string(file, " ");
1928 err |= control(file, "function", math_function,
1929 brw_inst_math_function(devinfo, inst), NULL);
1930
1931 } else if (opcode == BRW_OPCODE_SYNC) {
1932 string(file, " ");
1933 err |= control(file, "function", sync_function,
1934 brw_inst_cond_modifier(devinfo, inst), NULL);
1935
1936 } else if (!is_send(opcode)) {
1937 err |= control(file, "conditional modifier", conditional_modifier,
1938 brw_inst_cond_modifier(devinfo, inst), NULL);
1939
1940 /* If we're using the conditional modifier, print which flags reg is
1941 * used for it. Note that on gfx6+, the embedded-condition SEL and
1942 * control flow doesn't update flags.
1943 */
1944 if (brw_inst_cond_modifier(devinfo, inst) &&
1945 (devinfo->ver < 6 || (opcode != BRW_OPCODE_SEL &&
1946 opcode != BRW_OPCODE_CSEL &&
1947 opcode != BRW_OPCODE_IF &&
1948 opcode != BRW_OPCODE_WHILE))) {
1949 format(file, ".f%"PRIu64".%"PRIu64,
1950 devinfo->ver >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0,
1951 brw_inst_flag_subreg_nr(devinfo, inst));
1952 }
1953 }
1954
1955 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1956 string(file, "(");
1957 err |= control(file, "execution size", exec_size,
1958 brw_inst_exec_size(devinfo, inst), NULL);
1959 string(file, ")");
1960 }
1961
1962 if (opcode == BRW_OPCODE_SEND && devinfo->ver < 6)
1963 format(file, " %"PRIu64, brw_inst_base_mrf(devinfo, inst));
1964
1965 if (brw_has_uip(devinfo, opcode)) {
1966 /* Instructions that have UIP also have JIP. */
1967 pad(file, 16);
1968 string(file, "JIP: ");
1969 write_label(file, devinfo, root_label, offset, brw_inst_jip(devinfo, inst));
1970
1971 pad(file, 38);
1972 string(file, "UIP: ");
1973 write_label(file, devinfo, root_label, offset, brw_inst_uip(devinfo, inst));
1974 } else if (brw_has_jip(devinfo, opcode)) {
1975 int jip;
1976 if (devinfo->ver >= 7) {
1977 jip = brw_inst_jip(devinfo, inst);
1978 } else {
1979 jip = brw_inst_gfx6_jump_count(devinfo, inst);
1980 }
1981
1982 pad(file, 16);
1983 string(file, "JIP: ");
1984 write_label(file, devinfo, root_label, offset, jip);
1985 } else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_BREAK ||
1986 opcode == BRW_OPCODE_CONTINUE ||
1987 opcode == BRW_OPCODE_ELSE)) {
1988 pad(file, 16);
1989 format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst));
1990 pad(file, 32);
1991 format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst));
1992 } else if (devinfo->ver < 6 && (opcode == BRW_OPCODE_IF ||
1993 opcode == BRW_OPCODE_IFF ||
1994 opcode == BRW_OPCODE_HALT ||
1995 opcode == BRW_OPCODE_WHILE)) {
1996 pad(file, 16);
1997 format(file, "Jump: %d", brw_inst_gfx4_jump_count(devinfo, inst));
1998 } else if (devinfo->ver < 6 && opcode == BRW_OPCODE_ENDIF) {
1999 pad(file, 16);
2000 format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst));
2001 } else if (opcode == BRW_OPCODE_JMPI) {
2002 pad(file, 16);
2003 err |= src1(file, isa, inst);
2004 } else if (desc && desc->nsrc == 3) {
2005 pad(file, 16);
2006 err |= dest_3src(file, devinfo, inst);
2007
2008 pad(file, 32);
2009 err |= src0_3src(file, devinfo, inst);
2010
2011 pad(file, 48);
2012 err |= src1_3src(file, devinfo, inst);
2013
2014 pad(file, 64);
2015 err |= src2_3src(file, devinfo, inst);
2016 } else if (desc) {
2017 if (desc->ndst > 0) {
2018 pad(file, 16);
2019 err |= dest(file, isa, inst);
2020 }
2021
2022 if (desc->nsrc > 0) {
2023 pad(file, 32);
2024 err |= src0(file, isa, inst);
2025 }
2026
2027 if (desc->nsrc > 1) {
2028 pad(file, 48);
2029 err |= src1(file, isa, inst);
2030 }
2031 }
2032
2033 if (is_send(opcode)) {
2034 enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
2035
2036 bool has_imm_desc = false, has_imm_ex_desc = false;
2037 uint32_t imm_desc = 0, imm_ex_desc = 0;
2038 if (is_split_send(devinfo, opcode)) {
2039 pad(file, 64);
2040 if (brw_inst_send_sel_reg32_desc(devinfo, inst)) {
2041 /* show the indirect descriptor source */
2042 err |= src_send_desc_ia(file, devinfo, 0);
2043 } else {
2044 has_imm_desc = true;
2045 imm_desc = brw_inst_send_desc(devinfo, inst);
2046 fprintf(file, "0x%08"PRIx32, imm_desc);
2047 }
2048
2049 pad(file, 80);
2050 if (brw_inst_send_sel_reg32_ex_desc(devinfo, inst)) {
2051 /* show the indirect descriptor source */
2052 err |= src_send_desc_ia(file, devinfo,
2053 brw_inst_send_ex_desc_ia_subreg_nr(devinfo, inst));
2054 } else {
2055 has_imm_ex_desc = true;
2056 imm_ex_desc = brw_inst_sends_ex_desc(devinfo, inst);
2057 fprintf(file, "0x%08"PRIx32, imm_ex_desc);
2058 }
2059 } else {
2060 if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
2061 /* show the indirect descriptor source */
2062 pad(file, 48);
2063 err |= src1(file, isa, inst);
2064 pad(file, 64);
2065 } else {
2066 has_imm_desc = true;
2067 imm_desc = brw_inst_send_desc(devinfo, inst);
2068 pad(file, 48);
2069 }
2070
2071 /* Print message descriptor as immediate source */
2072 fprintf(file, "0x%08"PRIx64, inst->data[1] >> 32);
2073 }
2074
2075 newline(file);
2076 pad(file, 16);
2077 space = 0;
2078
2079 fprintf(file, " ");
2080 err |= control(file, "SFID", devinfo->ver >= 6 ? gfx6_sfid : gfx4_sfid,
2081 sfid, &space);
2082 string(file, " MsgDesc:");
2083
2084 if (!has_imm_desc) {
2085 format(file, " indirect");
2086 } else {
2087 bool unsupported = false;
2088 switch (sfid) {
2089 case BRW_SFID_MATH:
2090 err |= control(file, "math function", math_function,
2091 brw_inst_math_msg_function(devinfo, inst), &space);
2092 err |= control(file, "math saturate", math_saturate,
2093 brw_inst_math_msg_saturate(devinfo, inst), &space);
2094 err |= control(file, "math signed", math_signed,
2095 brw_inst_math_msg_signed_int(devinfo, inst), &space);
2096 err |= control(file, "math scalar", math_scalar,
2097 brw_inst_math_msg_data_type(devinfo, inst), &space);
2098 err |= control(file, "math precision", math_precision,
2099 brw_inst_math_msg_precision(devinfo, inst), &space);
2100 break;
2101 case BRW_SFID_SAMPLER:
2102 if (devinfo->ver >= 5) {
2103 err |= control(file, "sampler message", gfx5_sampler_msg_type,
2104 brw_sampler_desc_msg_type(devinfo, imm_desc),
2105 &space);
2106 err |= control(file, "sampler simd mode", gfx5_sampler_simd_mode,
2107 brw_sampler_desc_simd_mode(devinfo, imm_desc),
2108 &space);
2109 if (devinfo->ver >= 8 &&
2110 brw_sampler_desc_return_format(devinfo, imm_desc)) {
2111 string(file, " HP");
2112 }
2113 format(file, " Surface = %u Sampler = %u",
2114 brw_sampler_desc_binding_table_index(devinfo, imm_desc),
2115 brw_sampler_desc_sampler(devinfo, imm_desc));
2116 } else {
2117 format(file, " (bti %u, sampler %u, msg_type %u, ",
2118 brw_sampler_desc_binding_table_index(devinfo, imm_desc),
2119 brw_sampler_desc_sampler(devinfo, imm_desc),
2120 brw_sampler_desc_msg_type(devinfo, imm_desc));
2121 if (devinfo->verx10 != 45) {
2122 err |= control(file, "sampler target format",
2123 sampler_target_format,
2124 brw_sampler_desc_return_format(devinfo, imm_desc),
2125 NULL);
2126 }
2127 string(file, ")");
2128 }
2129 break;
2130 case GFX6_SFID_DATAPORT_SAMPLER_CACHE:
2131 case GFX6_SFID_DATAPORT_CONSTANT_CACHE:
2132 /* aka BRW_SFID_DATAPORT_READ on Gfx4-5 */
2133 if (devinfo->ver >= 6) {
2134 format(file, " (bti %u, msg_ctrl %u, msg_type %u, write_commit %u)",
2135 brw_dp_desc_binding_table_index(devinfo, imm_desc),
2136 brw_dp_desc_msg_control(devinfo, imm_desc),
2137 brw_dp_desc_msg_type(devinfo, imm_desc),
2138 devinfo->ver >= 7 ? 0u :
2139 brw_dp_write_desc_write_commit(devinfo, imm_desc));
2140 } else {
2141 bool is_965 = devinfo->verx10 == 40;
2142 err |= control(file, "DP read message type",
2143 is_965 ? gfx4_dp_read_port_msg_type :
2144 g45_dp_read_port_msg_type,
2145 brw_dp_read_desc_msg_type(devinfo, imm_desc),
2146 &space);
2147
2148 format(file, " MsgCtrl = 0x%u",
2149 brw_dp_read_desc_msg_control(devinfo, imm_desc));
2150
2151 format(file, " Surface = %u",
2152 brw_dp_desc_binding_table_index(devinfo, imm_desc));
2153 }
2154 break;
2155
2156 case GFX6_SFID_DATAPORT_RENDER_CACHE: {
2157 /* aka BRW_SFID_DATAPORT_WRITE on Gfx4-5 */
2158 unsigned msg_type = brw_fb_write_desc_msg_type(devinfo, imm_desc);
2159
2160 err |= control(file, "DP rc message type",
2161 dp_rc_msg_type(devinfo), msg_type, &space);
2162
2163 bool is_rt_write = msg_type ==
2164 (devinfo->ver >= 6 ? GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
2165 : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
2166
2167 if (is_rt_write) {
2168 err |= control(file, "RT message type", m_rt_write_subtype,
2169 brw_inst_rt_message_type(devinfo, inst), &space);
2170 if (devinfo->ver >= 6 && brw_inst_rt_slot_group(devinfo, inst))
2171 string(file, " Hi");
2172 if (brw_fb_write_desc_last_render_target(devinfo, imm_desc))
2173 string(file, " LastRT");
2174 if (devinfo->ver >= 10 &&
2175 brw_fb_write_desc_coarse_write(devinfo, imm_desc))
2176 string(file, " CoarseWrite");
2177 if (devinfo->ver < 7 &&
2178 brw_fb_write_desc_write_commit(devinfo, imm_desc))
2179 string(file, " WriteCommit");
2180 } else {
2181 format(file, " MsgCtrl = 0x%u",
2182 brw_fb_write_desc_msg_control(devinfo, imm_desc));
2183 }
2184
2185 format(file, " Surface = %u",
2186 brw_fb_desc_binding_table_index(devinfo, imm_desc));
2187 break;
2188 }
2189
2190 case BRW_SFID_URB: {
2191 unsigned opcode = brw_inst_urb_opcode(devinfo, inst);
2192
2193 format(file, " offset %"PRIu64, brw_inst_urb_global_offset(devinfo, inst));
2194
2195 space = 1;
2196
2197 err |= control(file, "urb opcode",
2198 devinfo->ver >= 7 ? gfx7_urb_opcode
2199 : gfx5_urb_opcode,
2200 opcode, &space);
2201
2202 if (devinfo->ver >= 7 &&
2203 brw_inst_urb_per_slot_offset(devinfo, inst)) {
2204 string(file, " per-slot");
2205 }
2206
2207 if (opcode == GFX8_URB_OPCODE_SIMD8_WRITE ||
2208 opcode == GFX8_URB_OPCODE_SIMD8_READ) {
2209 if (brw_inst_urb_channel_mask_present(devinfo, inst))
2210 string(file, " masked");
2211 } else if (opcode != GFX125_URB_OPCODE_FENCE) {
2212 err |= control(file, "urb swizzle", urb_swizzle,
2213 brw_inst_urb_swizzle_control(devinfo, inst),
2214 &space);
2215 }
2216
2217 if (devinfo->ver < 7) {
2218 err |= control(file, "urb allocate", urb_allocate,
2219 brw_inst_urb_allocate(devinfo, inst), &space);
2220 err |= control(file, "urb used", urb_used,
2221 brw_inst_urb_used(devinfo, inst), &space);
2222 }
2223 if (devinfo->ver < 8) {
2224 err |= control(file, "urb complete", urb_complete,
2225 brw_inst_urb_complete(devinfo, inst), &space);
2226 }
2227 break;
2228 }
2229 case BRW_SFID_THREAD_SPAWNER:
2230 break;
2231
2232 case BRW_SFID_MESSAGE_GATEWAY:
2233 format(file, " (%s)",
2234 gfx7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]);
2235 break;
2236
2237 case GFX12_SFID_SLM:
2238 case GFX12_SFID_TGM:
2239 case GFX12_SFID_UGM: {
2240 assert(devinfo->has_lsc);
2241 format(file, " (");
2242 const enum lsc_opcode op = lsc_msg_desc_opcode(devinfo, imm_desc);
2243 err |= control(file, "operation", lsc_operation,
2244 op, &space);
2245 format(file, ",");
2246 err |= control(file, "addr_size", lsc_addr_size,
2247 lsc_msg_desc_addr_size(devinfo, imm_desc),
2248 &space);
2249
2250 if (op == LSC_OP_FENCE) {
2251 format(file, ",");
2252 err |= control(file, "scope", lsc_fence_scope,
2253 lsc_fence_msg_desc_scope(devinfo, imm_desc),
2254 &space);
2255 format(file, ",");
2256 err |= control(file, "flush_type", lsc_flush_type,
2257 lsc_fence_msg_desc_flush_type(devinfo, imm_desc),
2258 &space);
2259 format(file, ",");
2260 err |= control(file, "backup_mode_fence_routing",
2261 lsc_backup_fence_routing,
2262 lsc_fence_msg_desc_backup_routing(devinfo, imm_desc),
2263 &space);
2264 } else {
2265 format(file, ",");
2266 err |= control(file, "data_size", lsc_data_size,
2267 lsc_msg_desc_data_size(devinfo, imm_desc),
2268 &space);
2269 format(file, ",");
2270 if (lsc_opcode_has_cmask(op)) {
2271 err |= control(file, "component_mask",
2272 lsc_cmask_str,
2273 lsc_msg_desc_cmask(devinfo, imm_desc),
2274 &space);
2275 } else {
2276 err |= control(file, "vector_size",
2277 lsc_vect_size_str,
2278 lsc_msg_desc_vect_size(devinfo, imm_desc),
2279 &space);
2280 if (lsc_msg_desc_transpose(devinfo, imm_desc))
2281 format(file, ", transpose");
2282 }
2283 switch(op) {
2284 case LSC_OP_LOAD_CMASK:
2285 case LSC_OP_LOAD:
2286 format(file, ",");
2287 err |= control(file, "cache_load",
2288 lsc_cache_load,
2289 lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
2290 &space);
2291 break;
2292 default:
2293 format(file, ",");
2294 err |= control(file, "cache_store",
2295 lsc_cache_store,
2296 lsc_msg_desc_cache_ctrl(devinfo, imm_desc),
2297 &space);
2298 break;
2299 }
2300 }
2301 format(file, " dst_len = %u,", lsc_msg_desc_dest_len(devinfo, imm_desc));
2302 format(file, " src0_len = %u,", lsc_msg_desc_src0_len(devinfo, imm_desc));
2303 format(file, " src1_len = %d", brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
2304 err |= control(file, "address_type", lsc_addr_surface_type,
2305 lsc_msg_desc_addr_type(devinfo, imm_desc), &space);
2306 format(file, " )");
2307 break;
2308 }
2309
2310 case GFX7_SFID_DATAPORT_DATA_CACHE:
2311 if (devinfo->ver >= 7) {
2312 format(file, " (");
2313 space = 0;
2314
2315 err |= control(file, "DP DC0 message type",
2316 dp_dc0_msg_type_gfx7,
2317 brw_dp_desc_msg_type(devinfo, imm_desc), &space);
2318
2319 format(file, ", bti %u, ",
2320 brw_dp_desc_binding_table_index(devinfo, imm_desc));
2321
2322 switch (brw_inst_dp_msg_type(devinfo, inst)) {
2323 case GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
2324 control(file, "atomic op", aop,
2325 brw_dp_desc_msg_control(devinfo, imm_desc) & 0xf,
2326 &space);
2327 break;
2328 case GFX7_DATAPORT_DC_OWORD_BLOCK_READ:
2329 case GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE: {
2330 unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
2331 assert(dp_oword_block_rw[msg_ctrl & 7]);
2332 format(file, "owords = %s, aligned = %d",
2333 dp_oword_block_rw[msg_ctrl & 7], (msg_ctrl >> 3) & 3);
2334 break;
2335 }
2336 default:
2337 format(file, "%u",
2338 brw_dp_desc_msg_control(devinfo, imm_desc));
2339 }
2340 format(file, ")");
2341 } else {
2342 unsupported = true;
2343 }
2344 break;
2345
2346 case HSW_SFID_DATAPORT_DATA_CACHE_1: {
2347 if (devinfo->ver >= 7) {
2348 format(file, " (");
2349 space = 0;
2350
2351 unsigned msg_ctrl = brw_dp_desc_msg_control(devinfo, imm_desc);
2352
2353 err |= control(file, "DP DC1 message type",
2354 dp_dc1_msg_type_hsw,
2355 brw_dp_desc_msg_type(devinfo, imm_desc), &space);
2356
2357 format(file, ", Surface = %u, ",
2358 brw_dp_desc_binding_table_index(devinfo, imm_desc));
2359
2360 switch (brw_inst_dp_msg_type(devinfo, inst)) {
2361 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
2362 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
2363 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
2364 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2365 FALLTHROUGH;
2366 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
2367 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
2368 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
2369 case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP:
2370 case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_INT_OP:
2371 control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
2372 break;
2373 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
2374 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
2375 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
2376 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE:
2377 case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE:
2378 case GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ: {
2379 static const char *simd_modes[] = { "4x2", "16", "8" };
2380 format(file, "SIMD%s, Mask = 0x%x",
2381 simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
2382 break;
2383 }
2384 case GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP:
2385 case GFX9_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_FLOAT_OP:
2386 case GFX12_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_HALF_FLOAT_OP:
2387 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
2388 control(file, "atomic float op", aop_float, msg_ctrl & 0xf,
2389 &space);
2390 break;
2391 case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE:
2392 case GFX9_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ:
2393 assert(dp_oword_block_rw[msg_ctrl & 7]);
2394 format(file, "owords = %s, aligned = %d",
2395 dp_oword_block_rw[msg_ctrl & 7], (msg_ctrl >> 3) & 3);
2396 break;
2397 default:
2398 format(file, "0x%x", msg_ctrl);
2399 }
2400 format(file, ")");
2401 } else {
2402 unsupported = true;
2403 }
2404 break;
2405 }
2406
2407 case GFX7_SFID_PIXEL_INTERPOLATOR:
2408 if (devinfo->ver >= 7) {
2409 format(file, " (%s, %s, 0x%02"PRIx64")",
2410 brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
2411 pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
2412 brw_inst_pi_message_data(devinfo, inst));
2413 } else {
2414 unsupported = true;
2415 }
2416 break;
2417
2418 case GEN_RT_SFID_RAY_TRACE_ACCELERATOR:
2419 if (devinfo->has_ray_tracing) {
2420 format(file, " SIMD%d,",
2421 brw_rt_trace_ray_desc_exec_size(devinfo, imm_desc));
2422 } else {
2423 unsupported = true;
2424 }
2425 break;
2426
2427 default:
2428 unsupported = true;
2429 break;
2430 }
2431
2432 if (unsupported)
2433 format(file, "unsupported shared function ID %d", sfid);
2434
2435 if (space)
2436 string(file, " ");
2437 }
2438 if (brw_sfid_is_lsc(sfid)) {
2439 lsc_disassemble_ex_desc(devinfo, imm_desc, imm_ex_desc, file);
2440 } else {
2441 if (has_imm_desc)
2442 format(file, "mlen %u", brw_message_desc_mlen(devinfo, imm_desc));
2443 if (has_imm_ex_desc) {
2444 format(file, " ex_mlen %u",
2445 brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
2446 }
2447 if (has_imm_desc)
2448 format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc));
2449 }
2450 }
2451 pad(file, 64);
2452 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
2453 string(file, "{");
2454 space = 1;
2455 err |= control(file, "access mode", access_mode,
2456 brw_inst_access_mode(devinfo, inst), &space);
2457 if (devinfo->ver >= 6) {
2458 err |= control(file, "write enable control", wectrl,
2459 brw_inst_mask_control(devinfo, inst), &space);
2460 } else {
2461 err |= control(file, "mask control", mask_ctrl,
2462 brw_inst_mask_control(devinfo, inst), &space);
2463 }
2464
2465 if (devinfo->ver < 12) {
2466 err |= control(file, "dependency control", dep_ctrl,
2467 ((brw_inst_no_dd_check(devinfo, inst) << 1) |
2468 brw_inst_no_dd_clear(devinfo, inst)), &space);
2469 }
2470
2471 if (devinfo->ver >= 6)
2472 err |= qtr_ctrl(file, devinfo, inst);
2473 else {
2474 if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
2475 desc && desc->ndst > 0 &&
2476 brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE &&
2477 brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) {
2478 format(file, " compr4");
2479 } else {
2480 err |= control(file, "compression control", compr_ctrl,
2481 brw_inst_qtr_control(devinfo, inst), &space);
2482 }
2483 }
2484
2485 if (devinfo->ver >= 12)
2486 err |= swsb(file, isa, inst);
2487
2488 err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
2489 err |= control(file, "thread control", thread_ctrl,
2490 (devinfo->ver >= 12 ? brw_inst_atomic_control(devinfo, inst) :
2491 brw_inst_thread_control(devinfo, inst)),
2492 &space);
2493 if (has_branch_ctrl(devinfo, opcode)) {
2494 err |= control(file, "branch ctrl", branch_ctrl,
2495 brw_inst_branch_control(devinfo, inst), &space);
2496 } else if (devinfo->ver >= 6) {
2497 err |= control(file, "acc write control", accwr,
2498 brw_inst_acc_wr_control(devinfo, inst), &space);
2499 }
2500 if (is_send(opcode))
2501 err |= control(file, "end of thread", end_of_thread,
2502 brw_inst_eot(devinfo, inst), &space);
2503 if (space)
2504 string(file, " ");
2505 string(file, "}");
2506 }
2507 string(file, ";");
2508 newline(file);
2509 return err;
2510 }
2511