Lines Matching +full:1 +full:c0
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
139 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR
140 tst \reg, #(1 << 5) @ CP15BEN bit set?
142 orr \reg, \reg, #(1 << 5) @ CP15 barrier instructions
143 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR
160 ldrb \tmp2, [\tmp1, #1]
170 sub ip, r1, ip, ror #1 @ poor man's kaslr seed, will
201 * These 7 nops along with the 1 nop immediately below for
223 W(b) 1f
233 1:
302 * additional 1MB of room for a possible appended DTB.
309 orrcc r4, r4, #1 @ remember we skipped cache_on
378 add r5, r5, r5, lsr #1
382 /* clamp to 32KB min and 1MB max */
383 cmp r5, #(1 << 15)
384 movlo r5, #(1 << 15)
385 cmp r5, #(1 << 20)
386 movhi r5, #(1 << 20)
396 * If returned value is 1, there is no ATAG at the location
400 cmp r0, #1
402 bic r0, r0, #1
449 bne 1f
484 mrc p15, 0, r1, c0, c1, 1 @ read ID_PFR1 register
486 mrrcne p15, 1, r3, r1, c14 @ read CNTVCT
506 1:
551 bne 1f
562 1:
585 1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
588 bhi 1b
638 1: ldr r1, [r11, #0] @ relocate entries in the GOT
645 blo 1b
657 1: ldr r1, [r11, #0] @ relocate entries in the GOT
663 blo 1b
667 1: str r0, [r2], #4 @ clear bss
672 blo 1b
679 tst r4, #1
680 bic r4, r4, #1
756 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
792 mcr p15, 0, r0, c6, c7, 1
795 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
796 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
797 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
800 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
801 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
807 mrc p15, 0, r0, c1, c0, 0 @ read control reg
809 orr r0, r0, #0x002d @ .... .... ..1. 11.1
810 orr r0, r0, #0x1000 @ ...1 .... .... ....
812 mcr p15, 0, r0, c1, c0, 0 @ write control reg
824 mcr p15, 0, r0, c2, c0, 0 @ cache on
825 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
828 mcr p15, 0, r0, c5, c0, 0 @ access permission
831 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
836 mrc p15, 0, r0, c1, c0, 0 @ read control reg
841 mcr p15, 0, r0, c1, c0, 0 @ write control reg
844 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
867 1: cmp r1, r9 @ if virt > start of RAM
872 str r1, [r0], #4 @ 1:1 mapping
875 bne 1b
901 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
903 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
904 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
910 mcr p15, 7, r0, c15, c0, 0
921 mrc p15, 0, r0, c1, c0, 0 @ read control reg
924 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
935 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
944 mrc p15, 0, r0, c1, c0, 0 @ read control reg
945 bic r0, r0, #1 << 28 @ clear SCTLR.TRE
949 orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
952 ARM_BE8( orr r0, r0, #1 << 25 ) @ big-endian page tables
953 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
954 orrne r0, r0, #1 @ MMU enabled
956 bic r6, r6, #1 << 31 @ 32-bit translation system
957 bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0
958 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
959 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
960 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
963 mcr p15, 0, r0, c1, c0, 0 @ load control register
964 mrc p15, 0, r0, c1, c0, 0 @ and read it back
977 mrc p15, 0, r0, c1, c0, 0 @ read control reg
989 mov r1, #-1
990 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
991 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
992 b 1f
994 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
995 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
1017 mrc p15, 0, r9, c0, c0 @ get processor ID
1031 1: ldr r1, [r12, #0] @ get value
1039 b 1b
1224 mrc p15, 0, r0, c1, c0
1226 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1234 mrc p15, 0, r0, c1, c0
1236 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1238 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1243 mrc p15, 0, r0, c1, c0
1245 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1253 mrc p15, 0, r0, c1, c0
1259 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1287 tst r4, #1
1289 mov r2, #1
1293 1: orr r3, r1, #63 << 26 @ 64 entries
1295 subs r3, r3, #1 << 26
1297 subs r1, r1, #1 << 5
1298 bcs 1b @ segments 7 to 0
1306 tst r4, #1
1316 tst r4, #1
1325 tst r4, #1
1327 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1335 sub r2, r1, #1 @ r2 := line size mask
1337 sub r11, r11, #1 @ end address is exclusive
1341 mcr p15, 0, r0, c7, c14, 1 @ Dcache clean/invalidate by VA
1352 tst r4, #1
1354 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate D cache
1355 bne 1b
1361 tst r4, #1
1365 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1372 tst r3, #1 << 14 @ test M bit
1373 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
1382 1:
1387 bne 1b
1396 tst r4, #1
1399 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1416 1: subs r1, r1, #1
1425 b 1b
1429 1: ldrb r2, [r0], #1
1434 3: subs r1, r1, #1
1440 bne 1b
1459 1: mov r0, #' '
1469 add r11, r11, #1
1471 bne 1b
1507 M_CLASS( add r4, r4, #1 ) @ enter in Thumb mode for M class
1531 lsrs r0, r0, #1
1546 mrc p15, 4, r0, c1, c0, 0 @ read HSCTLR
1548 mcr p15, 4, r0, c1, c0, 0 @ write HSCTLR
1564 @ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1576 mrc p15, 4, r1, c1, c0, 0 @ read HSCTLR
1578 beq 1f
1582 @ off just carrying on using the cached 1:1 mapping that the
1587 ARM( bic r1, r1, #(1 << 30) ) @ clear HSCTLR.TE
1588 THUMB( orr r1, r1, #(1 << 30) ) @ set HSCTLR.TE
1589 mcr p15, 4, r1, c1, c0, 0
1591 mcr p15, 4, r0, c12, c0, 0 @ set HYP vector base (HVBAR)
1598 @ 1:1 mapping as usual.
1600 1: mov r9, r4 @ preserve image base
1604 orr r4, r9, #1 @ restore image base and set LSB
1608 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
1610 orreq r4, r4, #1 @ set LSB if not