Lines Matching +full:12 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
29 #define CRn_shift 12
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
238 #define SYS_PAR_EL1_F BIT(0)
252 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
348 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
349 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
351 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
352 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
353 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
354 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
355 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
360 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
365 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
366 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
367 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
368 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
369 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
370 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
371 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
372 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
373 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
374 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
375 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
376 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
377 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
399 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
400 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
401 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
402 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
403 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
404 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
405 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
406 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
434 * n: 0-15
440 * n: 0-15
445 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
486 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
487 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
493 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
499 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
500 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
501 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
502 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
503 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
504 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
505 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
506 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
508 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
518 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
544 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
555 #define SCTLR_ELx_DSSBS (BIT(44))
556 #define SCTLR_ELx_ATA (BIT(43))
564 #define SCTLR_ELx_ITFSB (BIT(37))
565 #define SCTLR_ELx_ENIA (BIT(31))
566 #define SCTLR_ELx_ENIB (BIT(30))
567 #define SCTLR_ELx_ENDA (BIT(27))
568 #define SCTLR_ELx_EE (BIT(25))
569 #define SCTLR_ELx_IESB (BIT(21))
570 #define SCTLR_ELx_WXN (BIT(19))
571 #define SCTLR_ELx_ENDB (BIT(13))
572 #define SCTLR_ELx_I (BIT(12))
573 #define SCTLR_ELx_SA (BIT(3))
574 #define SCTLR_ELx_C (BIT(2))
575 #define SCTLR_ELx_A (BIT(1))
576 #define SCTLR_ELx_M (BIT(0))
582 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
583 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \
584 (BIT(29)))
593 #define SCTLR_EL1_ATA0 (BIT(42))
601 #define SCTLR_EL1_BT1 (BIT(36))
602 #define SCTLR_EL1_BT0 (BIT(35))
603 #define SCTLR_EL1_UCI (BIT(26))
604 #define SCTLR_EL1_E0E (BIT(24))
605 #define SCTLR_EL1_SPAN (BIT(23))
606 #define SCTLR_EL1_NTWE (BIT(18))
607 #define SCTLR_EL1_NTWI (BIT(16))
608 #define SCTLR_EL1_UCT (BIT(15))
609 #define SCTLR_EL1_DZE (BIT(14))
610 #define SCTLR_EL1_UMA (BIT(9))
611 #define SCTLR_EL1_SED (BIT(8))
612 #define SCTLR_EL1_ITD (BIT(7))
613 #define SCTLR_EL1_CP15BEN (BIT(5))
614 #define SCTLR_EL1_SA0 (BIT(4))
616 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
617 (BIT(29)))
657 #define ID_AA64ISAR0_SHA2_SHIFT 12
675 #define ID_AA64ISAR1_JSCVT_SHIFT 12
724 #define ID_AA64PFR0_EL3_SHIFT 12
743 #define ID_AA64PFR1_RASFRAC_SHIFT 12
790 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
828 #define ID_AA64MMFR1_HPD_SHIFT 12
848 #define ID_AA64MMFR2_IESB_SHIFT 12
858 #define ID_AA64DFR0_BRPS_SHIFT 12
877 #define ID_ISAR4_SMC_SHIFT 12
887 #define ID_ISAR0_CMPBRANCH_SHIFT 12
894 #define ID_ISAR5_SHA2_SHIFT 12
902 #define ID_ISAR6_SB_SHIFT 12
911 #define ID_MMFR0_SHARELVL_SHIFT 12
920 #define ID_MMFR4_CNP_SHIFT 12
929 #define ID_PFR0_STATE3_SHIFT 12
937 #define ID_DFR0_COPTRC_SHIFT 12
949 #define MVFR0_FPTRAP_SHIFT 12
958 #define MVFR1_SIMDINT_SHIFT 12
967 #define ID_PFR1_VIRTUALIZATION_SHIFT 12
1001 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */
1002 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */
1005 /* TCR EL1 Bit Definitions */
1006 #define SYS_TCR_EL1_TCMA1 (BIT(58))
1007 #define SYS_TCR_EL1_TCMA0 (BIT(57))
1010 #define SYS_GCR_EL1_RRND (BIT(16))
1022 /* TFSR{,E0}_EL1 bit definitions */
1029 #define SYS_MPIDR_SAFE_VAL (BIT(31))
1033 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
1053 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
1123 * set mask are set. Other bits are left as-is.