Lines Matching +full:can +full:- +full:clock +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
13 applications, and are all System-On-Chip (SOC) devices, as opposed
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
26 select ARCH_HAVE_CUSTOM_GPIO_H
27 select CPU_HAS_NO_BITFIELDS
28 select CPU_HAS_NO_CAS
29 select CPU_HAS_NO_MULDIV64
30 select GENERIC_CSUM
31 select GPIOLIB
32 select HAVE_LEGACY_CLK
41 select CPU_HAS_NO_BITFIELDS
42 select CPU_HAS_NO_CAS
43 select CPU_HAS_NO_MULDIV64
44 select CPU_HAS_NO_UNALIGNED
45 select GENERIC_CSUM
46 select CPU_NO_EFFICIENT_FFS
47 select HAVE_ARCH_HASH
52 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
57 select CPU_HAS_NO_BITFIELDS
58 select CPU_HAS_NO_CAS
59 select CPU_HAS_NO_UNALIGNED
60 select CPU_NO_EFFICIENT_FFS
64 System-On-Chip parts, and does not contain a paging MMU.
69 select FPU
70 select CPU_HAS_ADDRESS_SPACES
80 select FPU
81 select CPU_HAS_ADDRESS_SPACES
90 select FPU
91 select CPU_HAS_ADDRESS_SPACES
101 select FPU
102 select CPU_HAS_ADDRESS_SPACES
110 select M68000
117 select M68000
124 select M68000
136 Select the type of ColdFire System-on-Chip (SoC) that you want
142 select COLDFIRE_SW_A7
143 select HAVE_MBAR
144 select CPU_NO_EFFICIENT_FFS
151 select COLDFIRE_SW_A7
152 select HAVE_MBAR
153 select CPU_NO_EFFICIENT_FFS
160 select GENERIC_CLOCKEVENTS
161 select HAVE_CACHE_SPLIT
168 select GENERIC_CLOCKEVENTS
169 select HAVE_CACHE_SPLIT
170 select HAVE_IPSBAR
177 select COLDFIRE_SW_A7
178 select HAVE_MBAR
179 select CPU_NO_EFFICIENT_FFS
186 select COLDFIRE_SW_A7
187 select HAVE_MBAR
188 select CPU_NO_EFFICIENT_FFS
195 select M527x
196 select HAVE_CACHE_SPLIT
197 select HAVE_IPSBAR
198 select GENERIC_CLOCKEVENTS
205 select COLDFIRE_SW_A7
206 select HAVE_MBAR
207 select CPU_NO_EFFICIENT_FFS
214 select M527x
215 select HAVE_CACHE_SPLIT
216 select HAVE_IPSBAR
217 select GENERIC_CLOCKEVENTS
224 select GENERIC_CLOCKEVENTS
225 select HAVE_CACHE_SPLIT
226 select HAVE_IPSBAR
233 select COLDFIRE_SW_A7
234 select HAVE_CACHE_CB
235 select HAVE_MBAR
236 select CPU_NO_EFFICIENT_FFS
243 select M53xx
244 select HAVE_CACHE_CB
251 select M53xx
252 select HAVE_CACHE_CB
259 select COLDFIRE_SW_A7
260 select HAVE_CACHE_CB
261 select HAVE_MBAR
262 select CPU_NO_EFFICIENT_FFS
268 select M54xx
269 select MMU_COLDFIRE if MMU
270 select FPU if MMU
271 select HAVE_CACHE_CB
272 select HAVE_MBAR
273 select CPU_NO_EFFICIENT_FFS
279 select MMU_COLDFIRE if MMU
280 select FPU if MMU
281 select M54xx
282 select HAVE_CACHE_CB
283 select HAVE_MBAR
284 select CPU_NO_EFFICIENT_FFS
290 select MMU_COLDFIRE if MMU
291 select GENERIC_CLOCKEVENTS
292 select HAVE_CACHE_CB
305 select HAVE_PCI
317 At some point in the future, this will cause floating-point math
319 floating-point math coprocessor. Thrill-seekers and chronically
320 sleep-deprived psychotic hacker types can say Y now, everyone else
328 correct rounding, the emulator can (often) do the same but this
329 extra calculation can cost quite some time, so you can disable
338 This option prevents any floating-point instructions from being
341 kernel will only be usable on machines without a floating-point
343 needs to be executed whether a floating-point instruction in the
362 bool "Use read-modify-write instructions"
366 read-modify-write bus cycles. While this is faster than the
367 workaround of disabling interrupts, it can conflict with DMA
371 configuration where it should work are 68030-based Ataris, where it
380 select NEED_MULTIPLE_NODES
390 bool "Use write-through caching for 68060 supervisor accesses"
394 Copyback caching means that memory writes will be held in an on-chip
448 int "Set the core clock frequency"
460 Define the CPU clock frequency in use. This is the core clock
461 frequency, it may or may not be the same as the external clock
463 PLL and can have their frequency programmed at run time, others
504 bool "Write-through"
506 The ColdFire CPU cache is set into Write-through mode.
509 bool "Copy-back"
511 The ColdFire CPU cache is set into Copy-back mode.