Lines Matching +full:tx +full:- +full:mailbox +full:- +full:count

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
25 #define uPD98401_CHAN_RT	0x02000000 /*	RX/TX (0 TX, 1 RX) */
27 #define uPD98401_TX_READY	0x30000000 /* TX ready */
42 #define uPD98401_IA_TGT_CM	0	   /*	- Control Memory */
43 #define uPD98401_IA_TGT_SAR	1	   /*	- uPD98401 registers */
44 #define uPD98401_IA_TGT_PHY	3	   /*   - PHY device */
59 #define uPD98401_AAL5_UINFO	0xffff0000 /* user-supplied information */
110 #define uPD98401_MSH(n) (0x10+(n))	/* Mailbox n Start Address High */
111 #define uPD98401_MSL(n) (0x14+(n))	/* Mailbox n Start Address High */
112 #define uPD98401_MBA(n) (0x18+(n))	/* Mailbox n Bottom Address */
113 #define uPD98401_MTA(n) (0x1c+(n))	/* Mailbox n Tail Address */
114 #define uPD98401_MWA(n) (0x20+(n))	/* Mailbox n Write Address */
124 #define uPD98401_BURST16	0x00000800 /*	16-word burst */
125 #define uPD98401_BURST8		0x00000400 /*	 8-word burst */
126 #define uPD98401_BURST4		0x00000200 /*	 4-word burst */
127 #define uPD98401_BURST2		0x00000100 /*	 2-word burst */
148 #define uPD98401_INT_MF		0x000000f0 /* Mailbox Full */
150 #define uPD98401_INT_MM		0x0000000f /* Mailbox Modified */
184 #define uPD98401_PS_S		0x08	/* Scan - must be 0 (internal) */
194 #define uPD98401_TSR	0x40302	/* Time-Stamp Register */
203  * TX packet descriptor
220 #define uPD98401_TXPD_C10	0x00040000 /* insert CRC-10 */
222 #define uPD98401_TXPD_MB	0x00010000 /* TX mailbox number */
223 #define uPD98401_TXPD_UU	0x0000ff00 /* CPCS-UU */
228  * TX buffer descriptor
236  * TX VC table
239 /* 1st word has the same structure as in a TX packet descriptor */
266 #define uPD98401_RXVC_MB	0x00200000 /* RX mailbox number */
269 #define uPD98401_RXVC_UINFO	0x0000ffff /* user-supplied information */
285 #define uPD98401_RXVC_CURSEG	0x000007ff /* Current Segment count */