1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
7  * Adjustable divider clock implementation
10 #include <linux/clk-provider.h>
19  * DOC: basic adjustable divider clock that cannot gate
22  * prepare - clk_prepare only ensures that parents are prepared
23  * enable - clk_enable only ensures that parents are enabled
24  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
25  * parent - fixed parent.  No clk_set_parent support
28 static inline u32 clk_div_readl(struct clk_divider *divider)  in clk_div_readl()  argument
30 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_readl()
31 		return ioread32be(divider->reg);  in clk_div_readl()
33 	return readl(divider->reg);  in clk_div_readl()
36 static inline void clk_div_writel(struct clk_divider *divider, u32 val)  in clk_div_writel()  argument
38 	if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)  in clk_div_writel()
39 		iowrite32be(val, divider->reg);  in clk_div_writel()
41 		writel(val, divider->reg);  in clk_div_writel()
50 	for (clkt = table; clkt->div; clkt++)  in _get_table_maxdiv()
51 		if (clkt->div > maxdiv && clkt->val <= mask)  in _get_table_maxdiv()
52 			maxdiv = clkt->div;  in _get_table_maxdiv()
61 	for (clkt = table; clkt->div; clkt++)  in _get_table_mindiv()
62 		if (clkt->div < mindiv)  in _get_table_mindiv()
63 			mindiv = clkt->div;  in _get_table_mindiv()
84 	for (clkt = table; clkt->div; clkt++)  in _get_table_div()
85 		if (clkt->val == val)  in _get_table_div()
86 			return clkt->div;  in _get_table_div()
109 	for (clkt = table; clkt->div; clkt++)  in _get_table_val()
110 		if (clkt->div == div)  in _get_table_val()
111 			return clkt->val;  in _get_table_val()
126 	return div - 1;  in _get_val()
151 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_recalc_rate()  local
154 	val = clk_div_readl(divider) >> divider->shift;  in clk_divider_recalc_rate()
155 	val &= clk_div_mask(divider->width);  in clk_divider_recalc_rate()
157 	return divider_recalc_rate(hw, parent_rate, val, divider->table,  in clk_divider_recalc_rate()
158 				   divider->flags, divider->width);  in clk_divider_recalc_rate()
166 	for (clkt = table; clkt->div; clkt++)  in _is_valid_table_div()
167 		if (clkt->div == div)  in _is_valid_table_div()
187 	for (clkt = table; clkt->div; clkt++) {  in _round_up_table()
188 		if (clkt->div == div)  in _round_up_table()
189 			return clkt->div;  in _round_up_table()
190 		else if (clkt->div < div)  in _round_up_table()
193 		if ((clkt->div - div) < (up - div))  in _round_up_table()
194 			up = clkt->div;  in _round_up_table()
205 	for (clkt = table; clkt->div; clkt++) {  in _round_down_table()
206 		if (clkt->div == div)  in _round_down_table()
207 			return clkt->div;  in _round_down_table()
208 		else if (clkt->div > div)  in _round_down_table()
211 		if ((div - clkt->div) < (div - down))  in _round_down_table()
212 			down = clkt->div;  in _round_down_table()
253 	return (rate - up_rate) <= (down_rate - rate) ? up : down;  in _div_round_closest()
270 		return abs(rate - now) < abs(rate - best);  in _is_best_div()
312 	 * The maximum divider we can use without overflowing  in clk_divider_bestdiv()
323 			 * parent rate, so return the divider immediately.  in clk_divider_bestdiv()
367 	/* Even a read-only clock can propagate a rate change */  in divider_ro_round_rate_parent()
370 			return -EINVAL;  in divider_ro_round_rate_parent()
383 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_round_rate()  local
386 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in clk_divider_round_rate()
389 		val = clk_div_readl(divider) >> divider->shift;  in clk_divider_round_rate()
390 		val &= clk_div_mask(divider->width);  in clk_divider_round_rate()
392 		return divider_ro_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
393 					     divider->width, divider->flags,  in clk_divider_round_rate()
397 	return divider_round_rate(hw, rate, prate, divider->table,  in clk_divider_round_rate()
398 				  divider->width, divider->flags);  in clk_divider_round_rate()
410 		return -EINVAL;  in divider_get_val()
421 	struct clk_divider *divider = to_clk_divider(hw);  in clk_divider_set_rate()  local
426 	value = divider_get_val(rate, parent_rate, divider->table,  in clk_divider_set_rate()
427 				divider->width, divider->flags);  in clk_divider_set_rate()
431 	if (divider->lock)  in clk_divider_set_rate()
432 		spin_lock_irqsave(divider->lock, flags);  in clk_divider_set_rate()
434 		__acquire(divider->lock);  in clk_divider_set_rate()
436 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {  in clk_divider_set_rate()
437 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in clk_divider_set_rate()
439 		val = clk_div_readl(divider);  in clk_divider_set_rate()
440 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in clk_divider_set_rate()
442 	val |= (u32)value << divider->shift;  in clk_divider_set_rate()
443 	clk_div_writel(divider, val);  in clk_divider_set_rate()
445 	if (divider->lock)  in clk_divider_set_rate()
446 		spin_unlock_irqrestore(divider->lock, flags);  in clk_divider_set_rate()
448 		__release(divider->lock);  in clk_divider_set_rate()
480 			pr_warn("divider value exceeds LOWORD field\n");  in __clk_hw_register_divider()
481 			return ERR_PTR(-EINVAL);  in __clk_hw_register_divider()
485 	/* allocate the divider */  in __clk_hw_register_divider()
488 		return ERR_PTR(-ENOMEM);  in __clk_hw_register_divider()
505 	div->reg = reg;  in __clk_hw_register_divider()
506 	div->shift = shift;  in __clk_hw_register_divider()
507 	div->width = width;  in __clk_hw_register_divider()
508 	div->flags = clk_divider_flags;  in __clk_hw_register_divider()
509 	div->lock = lock;  in __clk_hw_register_divider()
510 	div->hw.init = &init;  in __clk_hw_register_divider()
511 	div->table = table;  in __clk_hw_register_divider()
514 	hw = &div->hw;  in __clk_hw_register_divider()
526  * clk_register_divider_table - register a table based divider clock with
531  * @flags: framework-specific flags
532  * @reg: register address to adjust divider
535  * @clk_divider_flags: divider-specific flags for this clock
536  * @table: array of divider/value pairs ending with a div set to 0
552 	return hw->clk;  in clk_register_divider_table()
573  * clk_hw_unregister_divider - unregister a clk divider
574  * @hw: hardware-specific clock data to unregister