Lines Matching +full:osc +full:- +full:bypass
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
19 #include <dt-bindings/clock/imx6qdl-clock.h>
23 static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
26 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
59 static const char *uart_sels[] = { "pll3_80m", "osc", };
60 static const char *ipg_per_sels[] = { "ipg", "osc", };
61 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
62 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
70 "ipu2", "vdo_axi", "osc", "gpu2d_core",
81 "dummy", "dummy", "dummy", "dummy", "osc",
83 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
149 return -ENOENT; in ldb_di_sel_by_clock_id()
160 return -ENOENT; in ldb_di_sel_by_clock_id()
172 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
173 "#clock-cells"); in of_assigned_ldb_sels()
175 rc = of_parse_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
176 "#clock-cells", index, &clkspec); in of_assigned_ldb_sels()
179 if (rc == -ENOENT) in of_assigned_ldb_sels()
190 rc = of_parse_phandle_with_args(node, "assigned-clocks", in of_assigned_ldb_sels()
191 "#clock-cells", index, &clkspec); in of_assigned_ldb_sels()
223 num_clocks = of_count_phandle_with_args(node, "assigned-clocks", in pll6_bypassed()
224 "#clock-cells"); in pll6_bypassed()
229 ret = of_parse_phandle_with_args(node, "assigned-clocks", in pll6_bypassed()
230 "#clock-cells", index, in pll6_bypassed()
240 /* PLL6 bypass is not part of the assigned clock list */ in pll6_bypassed()
244 ret = of_parse_phandle_with_args(node, "assigned-clock-parents", in pll6_bypassed()
245 "#clock-cells", index, &clkspec); in pll6_bypassed()
264 * bypass clock source, since there is no CG bit for mmdc_ch1.
270 clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk, in mmdc_ch1_disable()
271 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in mmdc_ch1_disable()
273 /* Disable pll3_sw_clk by selecting the bypass clock source */ in mmdc_ch1_disable()
283 /* Enable pll3_sw_clk by disabling the bypass */ in mmdc_ch1_reenable()
301 * to decide between the first and second 4-port mux:
303 * pll5_video_div 0 --|\
304 * pll2_pfd0_352m 1 --| |_
305 * pll2_pfd2_396m 2 --| | `-|\
306 * mmdc_ch1_axi 3 --|/ | |
307 * | |--
308 * pll3_usb_otg 4 --|\ | |
309 * 5 --| |_,-|/
310 * 6 --| |
311 * 7 --|/
313 * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
314 * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
345 (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in init_ldb_clks()
346 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) { in init_ldb_clks()
359 pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i, in init_ldb_clks()
395 /* Make sure PLL2 PFDs 0-2 are gated */ in disable_anatop_clocks()
398 if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) == in disable_anatop_clocks()
399 hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk) in disable_anatop_clocks()
405 /* Make sure PLL3 PFDs 0-3 are gated */ in disable_anatop_clocks()
442 clk_hw_data->num = IMX6QDL_CLK_END; in imx6q_clocks_init()
443 hws = clk_hw_data->hws; in imx6q_clocks_init()
449 hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0); in imx6q_clocks_init()
455 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); in imx6q_clocks_init()
477 hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f); in imx6q_clocks_init()
478 hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1); in imx6q_clocks_init()
479 hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3); in imx6q_clocks_init()
480 hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f); in imx6q_clocks_init()
481 hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f); in imx6q_clocks_init()
482 hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6q_clocks_init()
483 hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3); in imx6q_clocks_init()
493 /* Do not bypass PLLs initially */ in imx6q_clocks_init()
494 clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk); in imx6q_clocks_init()
495 clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk); in imx6q_clocks_init()
496 clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk); in imx6q_clocks_init()
497 clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk); in imx6q_clocks_init()
498 clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk); in imx6q_clocks_init()
499 clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk); in imx6q_clocks_init()
500 clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk); in imx6q_clocks_init()
511 * Bit 20 is the reserved and read-only bit, we do this only for: in imx6q_clocks_init()
512 * - Do nothing for usbphy clk_enable/disable in imx6q_clocks_init()
513 * - Keep refcount when do usbphy clk_enable/disable, in that case, in imx6q_clocks_init()
528 * different post-dividers that are all affected by the single bypass in imx6q_clocks_init()
531 * dynamically changing the bypass bit, will yield unexpected results. in imx6q_clocks_init()
533 * essentially static with the divider ratios reflecting the bypass in imx6q_clocks_init()
556 * lvds1_gate and lvds2_gate are pseudo-gates. Both can be in imx6q_clocks_init()
586 hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8); in imx6q_clocks_init()
648 * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware in imx6q_clocks_init()
917 clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000); in imx6q_clocks_init()
919 clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk); in imx6q_clocks_init()
921 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
922 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
923 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
924 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()
925 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk); in imx6q_clocks_init()
926 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk); in imx6q_clocks_init()
927 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk); in imx6q_clocks_init()
928 clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk); in imx6q_clocks_init()
935 clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk); in imx6q_clocks_init()
938 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk); in imx6q_clocks_init()
939 clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk); in imx6q_clocks_init()
946 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk); in imx6q_clocks_init()
948 ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk); in imx6q_clocks_init()
952 /* Audio-related clocks configuration */ in imx6q_clocks_init()
953 clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk); in imx6q_clocks_init()
957 clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk); in imx6q_clocks_init()
964 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
965 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
966 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init()
967 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
969 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk, in imx6q_clocks_init()
970 hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk); in imx6q_clocks_init()
971 clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk, in imx6q_clocks_init()
972 hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk); in imx6q_clocks_init()
973 clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk, in imx6q_clocks_init()
974 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); in imx6q_clocks_init()
979 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);