1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
90 #define imx_clk_divider(name, parent, reg, shift, width) \  argument
91 	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
93 #define imx_clk_divider2(name, parent, reg, shift, width) \  argument
94 	to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
96 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \  argument
97 	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
120 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \  argument
121 	to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
143 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
199 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
224 				 void __iomem *reg, u8 shift, u8 width,
228 			     u8 width, void __iomem *busy_reg, u8 busy_shift,
238 				  void __iomem *reg, u8 shift, u8 width,
242 			      u8 shift, u8 width, const char * const *parents,
249 	return hw->clk;  in to_clk()
265 			u8 shift, u8 width, const char * const *parents,  in imx_clk_hw_mux_ldb()  argument
270 			shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);  in imx_clk_hw_mux_ldb()
283 						u8 width)  in imx_clk_hw_divider()  argument
286 				       reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider()
292 						   u8 width, unsigned long flags)  in imx_clk_hw_divider_flags()  argument
295 				       reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider_flags()
299 		void __iomem *reg, u8 shift, u8 width)  in imx_clk_hw_divider2()  argument
303 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_divider2()
307 		const char *parent, void __iomem *reg, u8 shift, u8 width,  in imx_clk_divider2_flags()  argument
312 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_divider2_flags()
329 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,  in imx_dev_clk_hw_gate()
381 static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,  in imx_dev_clk_hw_gate_shared()
440 			u8 shift, u8 width, const char * const *parents,  in imx_clk_hw_mux()  argument
445 			width, 0, &imx_ccm_lock);  in imx_clk_hw_mux()
448 static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,  in imx_dev_clk_hw_mux()
450 			u8 width, const char * const *parents, int num_parents)  in imx_dev_clk_hw_mux()  argument
454 			reg, shift, width, 0, &imx_ccm_lock);  in imx_dev_clk_hw_mux()
458 			u8 shift, u8 width, const char * const *parents,  in imx_clk_mux2()  argument
463 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_mux2()
467 					     u8 shift, u8 width,  in imx_clk_hw_mux2()  argument
474 				   reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_mux2()
478 			void __iomem *reg, u8 shift, u8 width,  in imx_clk_mux_flags()  argument
483 			flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,  in imx_clk_mux_flags()
488 		void __iomem *reg, u8 shift, u8 width,  in imx_clk_hw_mux2_flags()  argument
494 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_mux2_flags()
498 		void __iomem *reg, u8 shift, u8 width,  in imx_clk_mux2_flags()  argument
504 			reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_mux2_flags()
509 						  u8 width,  in imx_clk_hw_mux_flags()  argument
516 				   reg, shift, width, 0, &imx_ccm_lock);  in imx_clk_hw_mux_flags()
519 static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,  in imx_dev_clk_hw_mux_flags()
522 						  u8 width,  in imx_dev_clk_hw_mux_flags()  argument
529 				   reg, shift, width, 0, &imx_ccm_lock);  in imx_dev_clk_hw_mux_flags()
601 		unsigned long flags, void __iomem *reg, u8 shift, u8 width,