Lines Matching +full:data +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
17 #include "clk-regmap.h"
18 #include "clk-pll.h"
19 #include "clk-mpll.h"
21 #include "meson-eeclk.h"
26 .data = &(struct meson_clk_pll_data){
30 .width = 1,
35 .width = 9,
40 .width = 5,
45 .width = 12,
50 .width = 1,
55 .width = 1,
69 .data = &(struct clk_regmap_div_data){
72 .width = 2,
90 .data = &(struct meson_clk_pll_data){
94 .width = 1,
99 .width = 9,
104 .width = 5,
109 .width = 1,
114 .width = 1,
128 .data = &(struct clk_regmap_div_data){
131 .width = 2,
187 .data = &(struct meson_clk_pll_data){
191 .width = 1,
196 .width = 9,
201 .width = 5,
206 .width = 10,
211 .width = 1,
216 .width = 1,
233 .data = &(struct clk_regmap_div_data){
236 .width = 2,
259 .data = &(struct meson_clk_pll_data){
263 .width = 1,
268 .width = 9,
273 .width = 5,
278 .width = 13,
283 .width = 1,
288 .width = 1,
306 .data = &(struct clk_regmap_div_data){
309 .width = 2,
335 .data = &(struct clk_regmap_gate_data){
362 .data = &(struct clk_regmap_gate_data){
381 * b) CCF has a clock hand-off mechanism to make the sure the
400 .data = &(struct clk_regmap_gate_data){
426 .data = &(struct clk_regmap_gate_data){
454 .data = &(struct clk_regmap_gate_data){
469 .data = &(struct clk_regmap_div_data){
472 .width = 1,
485 .data = &(struct meson_clk_mpll_data){
489 .width = 14,
494 .width = 1,
499 .width = 9,
504 .width = 1,
520 .data = &(struct clk_regmap_gate_data){
536 .data = &(struct meson_clk_mpll_data){
540 .width = 14,
545 .width = 1,
550 .width = 9,
555 .width = 1,
571 .data = &(struct clk_regmap_gate_data){
587 .data = &(struct meson_clk_mpll_data){
591 .width = 14,
596 .width = 1,
601 .width = 9,
606 .width = 1,
611 .width = 1,
627 .data = &(struct clk_regmap_gate_data){
643 .data = &(struct meson_clk_mpll_data){
647 .width = 14,
652 .width = 1,
657 .width = 9,
662 .width = 1,
678 .data = &(struct clk_regmap_gate_data){
712 .data = &(struct meson_clk_pll_data){
716 .width = 1,
721 .width = 9,
726 .width = 5,
731 .width = 12,
736 .width = 1,
741 .width = 1,
758 .data = &(struct clk_regmap_div_data){
761 .width = 2,
776 .data = &(struct clk_regmap_div_data){
779 .width = 2,
794 .data = &(struct clk_regmap_mux_data){
811 .data = &(struct clk_regmap_mux_data){
828 .data = &(struct clk_regmap_gate_data){
843 .data = &(struct clk_regmap_gate_data){
868 .data = &(struct clk_regmap_mux_data){
883 .data = &(struct clk_regmap_div_data){
886 .width = 7,
900 .data = &(struct clk_regmap_gate_data){
931 .data = &(struct clk_regmap_mux_data){
946 .data = &(struct clk_regmap_div_data){
949 .width = 7,
964 .data = &(struct clk_regmap_gate_data){
981 .data = &(struct clk_regmap_mux_data){
996 .data = &(struct clk_regmap_div_data){
999 .width = 7,
1014 .data = &(struct clk_regmap_gate_data){
1046 .data = &(struct clk_regmap_mux_data){
1067 .data = &(struct clk_regmap_div_data){
1070 .width = 11,
1084 .data = &(struct clk_regmap_gate_data){
1354 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
1361 .name = "axg-clkc",