Lines Matching +full:common +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
18 * command. Please be aware that this setting may result in read pre-fetching
29 #include <linux/dma-mapping.h>
39 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
41 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
51 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
56 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
61 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
66 return FSL_DMA_IN(chan, &chan->regs->mr, 32); in get_mr()
71 FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); in set_cdar()
76 return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; in get_cdar()
81 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32); in set_bcr()
86 return FSL_DMA_IN(chan, &chan->regs->bcr, 32); in get_bcr()
96 hw->count = CPU_TO_DMA(chan, count, 32); in set_desc_cnt()
104 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) in set_desc_src()
106 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); in set_desc_src()
114 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) in set_desc_dst()
116 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); in set_desc_dst()
124 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) in set_desc_next()
126 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); in set_desc_next()
133 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) in set_ld_eol()
136 desc->hw.next_ln_addr = CPU_TO_DMA(chan, in set_ld_eol()
137 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL in set_ld_eol()
150 switch (chan->feature & FSL_DMA_IP_MASK) { in dma_init()
153 * EIE - Error interrupt enable in dma_init()
154 * EOLNIE - End of links interrupt enable in dma_init()
155 * BWC - Bandwidth sharing among channels in dma_init()
162 * EOTIE - End-of-transfer interrupt enable in dma_init()
163 * PRC_RM - PCI read multiple in dma_init()
180 * - the CDAR register must point to the start descriptor
181 * - the MRn[CS] bit must be cleared
185 u32 mode; in dma_start() local
187 mode = get_mr(chan); in dma_start()
189 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { in dma_start()
191 mode |= FSL_DMA_MR_EMP_EN; in dma_start()
193 mode &= ~FSL_DMA_MR_EMP_EN; in dma_start()
196 if (chan->feature & FSL_DMA_CHAN_START_EXT) { in dma_start()
197 mode |= FSL_DMA_MR_EMS_EN; in dma_start()
199 mode &= ~FSL_DMA_MR_EMS_EN; in dma_start()
200 mode |= FSL_DMA_MR_CS; in dma_start()
203 set_mr(chan, mode); in dma_start()
208 u32 mode; in dma_halt() local
211 /* read the mode register */ in dma_halt()
212 mode = get_mr(chan); in dma_halt()
219 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { in dma_halt()
220 mode |= FSL_DMA_MR_CA; in dma_halt()
221 set_mr(chan, mode); in dma_halt()
223 mode &= ~FSL_DMA_MR_CA; in dma_halt()
227 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); in dma_halt()
228 set_mr(chan, mode); in dma_halt()
243 * fsl_chan_set_src_loop_size - Set source address hold transfer size
255 u32 mode; in fsl_chan_set_src_loop_size() local
257 mode = get_mr(chan); in fsl_chan_set_src_loop_size()
261 mode &= ~FSL_DMA_MR_SAHE; in fsl_chan_set_src_loop_size()
267 mode &= ~FSL_DMA_MR_SAHTS_MASK; in fsl_chan_set_src_loop_size()
268 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); in fsl_chan_set_src_loop_size()
272 set_mr(chan, mode); in fsl_chan_set_src_loop_size()
276 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
288 u32 mode; in fsl_chan_set_dst_loop_size() local
290 mode = get_mr(chan); in fsl_chan_set_dst_loop_size()
294 mode &= ~FSL_DMA_MR_DAHE; in fsl_chan_set_dst_loop_size()
300 mode &= ~FSL_DMA_MR_DAHTS_MASK; in fsl_chan_set_dst_loop_size()
301 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); in fsl_chan_set_dst_loop_size()
305 set_mr(chan, mode); in fsl_chan_set_dst_loop_size()
309 * fsl_chan_set_request_count - Set DMA Request Count for external control
322 u32 mode; in fsl_chan_set_request_count() local
326 mode = get_mr(chan); in fsl_chan_set_request_count()
327 mode &= ~FSL_DMA_MR_BWC_MASK; in fsl_chan_set_request_count()
328 mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK; in fsl_chan_set_request_count()
330 set_mr(chan, mode); in fsl_chan_set_request_count()
334 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
345 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; in fsl_chan_toggle_ext_pause()
347 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; in fsl_chan_toggle_ext_pause()
351 * fsl_chan_toggle_ext_start - Toggle channel external start status
363 chan->feature |= FSL_DMA_CHAN_START_EXT; in fsl_chan_toggle_ext_start()
365 chan->feature &= ~FSL_DMA_CHAN_START_EXT; in fsl_chan_toggle_ext_start()
373 return -EINVAL; in fsl_dma_external_start()
384 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); in append_ld_queue()
386 if (list_empty(&chan->ld_pending)) in append_ld_queue()
393 * This will un-set the EOL bit of the existing transaction, and the in append_ld_queue()
396 set_desc_next(chan, &tail->hw, desc->async_tx.phys); in append_ld_queue()
403 list_splice_tail_init(&desc->tx_list, &chan->ld_pending); in append_ld_queue()
408 struct fsldma_chan *chan = to_fsl_chan(tx->chan); in fsl_dma_tx_submit()
411 dma_cookie_t cookie = -EINVAL; in fsl_dma_tx_submit()
413 spin_lock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
416 if (unlikely(chan->pm_state != RUNNING)) { in fsl_dma_tx_submit()
418 spin_unlock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
419 return -1; in fsl_dma_tx_submit()
427 list_for_each_entry(child, &desc->tx_list, node) { in fsl_dma_tx_submit()
428 cookie = dma_cookie_assign(&child->async_tx); in fsl_dma_tx_submit()
434 spin_unlock_bh(&chan->desc_lock); in fsl_dma_tx_submit()
440 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
447 list_del(&desc->node); in fsl_dma_free_descriptor()
449 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); in fsl_dma_free_descriptor()
453 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
456 * Return - The descriptor allocated. NULL for failed.
463 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc); in fsl_dma_alloc_descriptor()
469 INIT_LIST_HEAD(&desc->tx_list); in fsl_dma_alloc_descriptor()
470 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in fsl_dma_alloc_descriptor()
471 desc->async_tx.tx_submit = fsl_dma_tx_submit; in fsl_dma_alloc_descriptor()
472 desc->async_tx.phys = pdesc; in fsl_dma_alloc_descriptor()
480 * fsldma_clean_completed_descriptor - free all descriptors which
492 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) in fsldma_clean_completed_descriptor()
493 if (async_tx_test_ack(&desc->async_tx)) in fsldma_clean_completed_descriptor()
498 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
509 struct dma_async_tx_descriptor *txd = &desc->async_tx; in fsldma_run_tx_complete_actions()
512 BUG_ON(txd->cookie < 0); in fsldma_run_tx_complete_actions()
514 if (txd->cookie > 0) { in fsldma_run_tx_complete_actions()
515 ret = txd->cookie; in fsldma_run_tx_complete_actions()
529 * fsldma_clean_running_descriptor - move the completed descriptor from
541 list_del(&desc->node); in fsldma_clean_running_descriptor()
547 if (!async_tx_test_ack(&desc->async_tx)) { in fsldma_clean_running_descriptor()
552 list_add_tail(&desc->node, &chan->ld_completed); in fsldma_clean_running_descriptor()
556 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); in fsldma_clean_running_descriptor()
560 * fsl_chan_xfer_ld_queue - transfer any pending transactions
564 * LOCKING: must hold chan->desc_lock
574 if (list_empty(&chan->ld_pending)) { in fsl_chan_xfer_ld_queue()
584 if (!chan->idle) { in fsl_chan_xfer_ld_queue()
599 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); in fsl_chan_xfer_ld_queue()
600 list_splice_tail_init(&chan->ld_pending, &chan->ld_running); in fsl_chan_xfer_ld_queue()
607 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { in fsl_chan_xfer_ld_queue()
608 u32 mode; in fsl_chan_xfer_ld_queue() local
610 mode = get_mr(chan); in fsl_chan_xfer_ld_queue()
611 mode &= ~FSL_DMA_MR_CS; in fsl_chan_xfer_ld_queue()
612 set_mr(chan, mode); in fsl_chan_xfer_ld_queue()
619 set_cdar(chan, desc->async_tx.phys); in fsl_chan_xfer_ld_queue()
623 chan->idle = false; in fsl_chan_xfer_ld_queue()
627 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
645 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { in fsldma_cleanup_descriptors()
658 if (desc->async_tx.phys == curr_phys) { in fsldma_cleanup_descriptors()
678 chan->common.completed_cookie = cookie; in fsldma_cleanup_descriptors()
682 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
687 * Return - The number of descriptors allocated.
694 if (chan->desc_pool) in fsl_dma_alloc_chan_resources()
701 chan->desc_pool = dma_pool_create(chan->name, chan->dev, in fsl_dma_alloc_chan_resources()
704 if (!chan->desc_pool) { in fsl_dma_alloc_chan_resources()
706 return -ENOMEM; in fsl_dma_alloc_chan_resources()
714 * fsldma_free_desc_list - Free all descriptors in a queue
718 * LOCKING: must hold chan->desc_lock
739 * fsl_dma_free_chan_resources - Free all resources of the channel.
747 spin_lock_bh(&chan->desc_lock); in fsl_dma_free_chan_resources()
749 fsldma_free_desc_list(chan, &chan->ld_pending); in fsl_dma_free_chan_resources()
750 fsldma_free_desc_list(chan, &chan->ld_running); in fsl_dma_free_chan_resources()
751 fsldma_free_desc_list(chan, &chan->ld_completed); in fsl_dma_free_chan_resources()
752 spin_unlock_bh(&chan->desc_lock); in fsl_dma_free_chan_resources()
754 dma_pool_destroy(chan->desc_pool); in fsl_dma_free_chan_resources()
755 chan->desc_pool = NULL; in fsl_dma_free_chan_resources()
786 set_desc_cnt(chan, &new->hw, copy); in fsl_dma_prep_memcpy()
787 set_desc_src(chan, &new->hw, dma_src); in fsl_dma_prep_memcpy()
788 set_desc_dst(chan, &new->hw, dma_dst); in fsl_dma_prep_memcpy()
793 set_desc_next(chan, &prev->hw, new->async_tx.phys); in fsl_dma_prep_memcpy()
795 new->async_tx.cookie = 0; in fsl_dma_prep_memcpy()
796 async_tx_ack(&new->async_tx); in fsl_dma_prep_memcpy()
799 len -= copy; in fsl_dma_prep_memcpy()
804 list_add_tail(&new->node, &first->tx_list); in fsl_dma_prep_memcpy()
807 new->async_tx.flags = flags; /* client is in control of this ack */ in fsl_dma_prep_memcpy()
808 new->async_tx.cookie = -EBUSY; in fsl_dma_prep_memcpy()
810 /* Set End-of-link to the last link descriptor of new list */ in fsl_dma_prep_memcpy()
813 return &first->async_tx; in fsl_dma_prep_memcpy()
819 fsldma_free_desc_list_reverse(chan, &first->tx_list); in fsl_dma_prep_memcpy()
828 return -EINVAL; in fsl_dma_device_terminate_all()
832 spin_lock_bh(&chan->desc_lock); in fsl_dma_device_terminate_all()
838 fsldma_free_desc_list(chan, &chan->ld_pending); in fsl_dma_device_terminate_all()
839 fsldma_free_desc_list(chan, &chan->ld_running); in fsl_dma_device_terminate_all()
840 fsldma_free_desc_list(chan, &chan->ld_completed); in fsl_dma_device_terminate_all()
841 chan->idle = true; in fsl_dma_device_terminate_all()
843 spin_unlock_bh(&chan->desc_lock); in fsl_dma_device_terminate_all()
854 return -EINVAL; in fsl_dma_device_config()
859 if (!chan->set_request_count) in fsl_dma_device_config()
860 return -ENXIO; in fsl_dma_device_config()
863 if (config->direction == DMA_MEM_TO_DEV) in fsl_dma_device_config()
864 size = config->dst_addr_width * config->dst_maxburst; in fsl_dma_device_config()
866 size = config->src_addr_width * config->src_maxburst; in fsl_dma_device_config()
868 chan->set_request_count(chan, size); in fsl_dma_device_config()
874 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
881 spin_lock_bh(&chan->desc_lock); in fsl_dma_memcpy_issue_pending()
883 spin_unlock_bh(&chan->desc_lock); in fsl_dma_memcpy_issue_pending()
887 * fsl_tx_status - Determine the DMA status
901 spin_lock_bh(&chan->desc_lock); in fsl_tx_status()
903 spin_unlock_bh(&chan->desc_lock); in fsl_tx_status()
908 /*----------------------------------------------------------------------------*/
910 /*----------------------------------------------------------------------------*/
947 chan_dbg(chan, "irq: End-of-Chain link INT\n"); in fsldma_chan_irq()
952 * If it current transfer is the end-of-transfer, in fsldma_chan_irq()
957 chan_dbg(chan, "irq: End-of-link INT\n"); in fsldma_chan_irq()
974 tasklet_schedule(&chan->tasklet); in fsldma_chan_irq()
985 spin_lock(&chan->desc_lock); in dma_do_tasklet()
988 chan->idle = true; in dma_do_tasklet()
993 spin_unlock(&chan->desc_lock); in dma_do_tasklet()
1006 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) in fsldma_ctrl_irq()
1007 : in_le32(fdev->regs); in fsldma_ctrl_irq()
1009 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); in fsldma_ctrl_irq()
1012 chan = fdev->chan[i]; in fsldma_ctrl_irq()
1017 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); in fsldma_ctrl_irq()
1034 if (fdev->irq) { in fsldma_free_irqs()
1035 dev_dbg(fdev->dev, "free per-controller IRQ\n"); in fsldma_free_irqs()
1036 free_irq(fdev->irq, fdev); in fsldma_free_irqs()
1041 chan = fdev->chan[i]; in fsldma_free_irqs()
1042 if (chan && chan->irq) { in fsldma_free_irqs()
1043 chan_dbg(chan, "free per-channel IRQ\n"); in fsldma_free_irqs()
1044 free_irq(chan->irq, chan); in fsldma_free_irqs()
1055 /* if we have a per-controller IRQ, use that */ in fsldma_request_irqs()
1056 if (fdev->irq) { in fsldma_request_irqs()
1057 dev_dbg(fdev->dev, "request per-controller IRQ\n"); in fsldma_request_irqs()
1058 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, in fsldma_request_irqs()
1059 "fsldma-controller", fdev); in fsldma_request_irqs()
1063 /* no per-controller IRQ, use the per-channel IRQs */ in fsldma_request_irqs()
1065 chan = fdev->chan[i]; in fsldma_request_irqs()
1069 if (!chan->irq) { in fsldma_request_irqs()
1071 ret = -ENODEV; in fsldma_request_irqs()
1075 chan_dbg(chan, "request per-channel IRQ\n"); in fsldma_request_irqs()
1076 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, in fsldma_request_irqs()
1077 "fsldma-chan", chan); in fsldma_request_irqs()
1079 chan_err(chan, "unable to request per-channel IRQ\n"); in fsldma_request_irqs()
1087 for (/* none */; i >= 0; i--) { in fsldma_request_irqs()
1088 chan = fdev->chan[i]; in fsldma_request_irqs()
1092 if (!chan->irq) in fsldma_request_irqs()
1095 free_irq(chan->irq, chan); in fsldma_request_irqs()
1101 /*----------------------------------------------------------------------------*/
1103 /*----------------------------------------------------------------------------*/
1115 err = -ENOMEM; in fsl_dma_chan_probe()
1120 chan->regs = of_iomap(node, 0); in fsl_dma_chan_probe()
1121 if (!chan->regs) { in fsl_dma_chan_probe()
1122 dev_err(fdev->dev, "unable to ioremap registers\n"); in fsl_dma_chan_probe()
1123 err = -ENOMEM; in fsl_dma_chan_probe()
1129 dev_err(fdev->dev, "unable to find 'reg' property\n"); in fsl_dma_chan_probe()
1133 chan->feature = feature; in fsl_dma_chan_probe()
1134 if (!fdev->feature) in fsl_dma_chan_probe()
1135 fdev->feature = chan->feature; in fsl_dma_chan_probe()
1141 WARN_ON(fdev->feature != chan->feature); in fsl_dma_chan_probe()
1143 chan->dev = fdev->dev; in fsl_dma_chan_probe()
1144 chan->id = (res.start & 0xfff) < 0x300 ? in fsl_dma_chan_probe()
1145 ((res.start - 0x100) & 0xfff) >> 7 : in fsl_dma_chan_probe()
1146 ((res.start - 0x200) & 0xfff) >> 7; in fsl_dma_chan_probe()
1147 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { in fsl_dma_chan_probe()
1148 dev_err(fdev->dev, "too many channels for device\n"); in fsl_dma_chan_probe()
1149 err = -EINVAL; in fsl_dma_chan_probe()
1153 fdev->chan[chan->id] = chan; in fsl_dma_chan_probe()
1154 tasklet_setup(&chan->tasklet, dma_do_tasklet); in fsl_dma_chan_probe()
1155 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); in fsl_dma_chan_probe()
1163 switch (chan->feature & FSL_DMA_IP_MASK) { in fsl_dma_chan_probe()
1165 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; in fsl_dma_chan_probe()
1168 chan->toggle_ext_start = fsl_chan_toggle_ext_start; in fsl_dma_chan_probe()
1169 chan->set_src_loop_size = fsl_chan_set_src_loop_size; in fsl_dma_chan_probe()
1170 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; in fsl_dma_chan_probe()
1171 chan->set_request_count = fsl_chan_set_request_count; in fsl_dma_chan_probe()
1174 spin_lock_init(&chan->desc_lock); in fsl_dma_chan_probe()
1175 INIT_LIST_HEAD(&chan->ld_pending); in fsl_dma_chan_probe()
1176 INIT_LIST_HEAD(&chan->ld_running); in fsl_dma_chan_probe()
1177 INIT_LIST_HEAD(&chan->ld_completed); in fsl_dma_chan_probe()
1178 chan->idle = true; in fsl_dma_chan_probe()
1180 chan->pm_state = RUNNING; in fsl_dma_chan_probe()
1183 chan->common.device = &fdev->common; in fsl_dma_chan_probe()
1184 dma_cookie_init(&chan->common); in fsl_dma_chan_probe()
1187 chan->irq = irq_of_parse_and_map(node, 0); in fsl_dma_chan_probe()
1190 list_add_tail(&chan->common.device_node, &fdev->common.channels); in fsl_dma_chan_probe()
1192 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, in fsl_dma_chan_probe()
1193 chan->irq ? chan->irq : fdev->irq); in fsl_dma_chan_probe()
1198 iounmap(chan->regs); in fsl_dma_chan_probe()
1207 irq_dispose_mapping(chan->irq); in fsl_dma_chan_remove()
1208 list_del(&chan->common.device_node); in fsl_dma_chan_remove()
1209 iounmap(chan->regs); in fsl_dma_chan_remove()
1222 err = -ENOMEM; in fsldma_of_probe()
1226 fdev->dev = &op->dev; in fsldma_of_probe()
1227 INIT_LIST_HEAD(&fdev->common.channels); in fsldma_of_probe()
1230 fdev->regs = of_iomap(op->dev.of_node, 0); in fsldma_of_probe()
1231 if (!fdev->regs) { in fsldma_of_probe()
1232 dev_err(&op->dev, "unable to ioremap registers\n"); in fsldma_of_probe()
1233 err = -ENOMEM; in fsldma_of_probe()
1238 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); in fsldma_of_probe()
1240 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); in fsldma_of_probe()
1241 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); in fsldma_of_probe()
1242 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; in fsldma_of_probe()
1243 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; in fsldma_of_probe()
1244 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; in fsldma_of_probe()
1245 fdev->common.device_tx_status = fsl_tx_status; in fsldma_of_probe()
1246 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; in fsldma_of_probe()
1247 fdev->common.device_config = fsl_dma_device_config; in fsldma_of_probe()
1248 fdev->common.device_terminate_all = fsl_dma_device_terminate_all; in fsldma_of_probe()
1249 fdev->common.dev = &op->dev; in fsldma_of_probe()
1251 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS; in fsldma_of_probe()
1252 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS; in fsldma_of_probe()
1253 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsldma_of_probe()
1254 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; in fsldma_of_probe()
1256 dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); in fsldma_of_probe()
1265 for_each_child_of_node(op->dev.of_node, child) { in fsldma_of_probe()
1266 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { in fsldma_of_probe()
1269 "fsl,eloplus-dma-channel"); in fsldma_of_probe()
1272 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { in fsldma_of_probe()
1275 "fsl,elo-dma-channel"); in fsldma_of_probe()
1282 * If we have a per-controller interrupt, we prefer that to the in fsldma_of_probe()
1283 * per-channel interrupts to reduce the number of shared interrupt in fsldma_of_probe()
1288 dev_err(fdev->dev, "unable to request IRQs\n"); in fsldma_of_probe()
1292 dma_async_device_register(&fdev->common); in fsldma_of_probe()
1297 if (fdev->chan[i]) in fsldma_of_probe()
1298 fsl_dma_chan_remove(fdev->chan[i]); in fsldma_of_probe()
1300 irq_dispose_mapping(fdev->irq); in fsldma_of_probe()
1301 iounmap(fdev->regs); in fsldma_of_probe()
1314 dma_async_device_unregister(&fdev->common); in fsldma_of_remove()
1319 if (fdev->chan[i]) in fsldma_of_remove()
1320 fsl_dma_chan_remove(fdev->chan[i]); in fsldma_of_remove()
1322 irq_dispose_mapping(fdev->irq); in fsldma_of_remove()
1324 iounmap(fdev->regs); in fsldma_of_remove()
1338 chan = fdev->chan[i]; in fsldma_suspend_late()
1342 spin_lock_bh(&chan->desc_lock); in fsldma_suspend_late()
1343 if (unlikely(!chan->idle)) in fsldma_suspend_late()
1345 chan->regs_save.mr = get_mr(chan); in fsldma_suspend_late()
1346 chan->pm_state = SUSPENDED; in fsldma_suspend_late()
1347 spin_unlock_bh(&chan->desc_lock); in fsldma_suspend_late()
1352 for (; i >= 0; i--) { in fsldma_suspend_late()
1353 chan = fdev->chan[i]; in fsldma_suspend_late()
1356 chan->pm_state = RUNNING; in fsldma_suspend_late()
1357 spin_unlock_bh(&chan->desc_lock); in fsldma_suspend_late()
1359 return -EBUSY; in fsldma_suspend_late()
1366 u32 mode; in fsldma_resume_early() local
1370 chan = fdev->chan[i]; in fsldma_resume_early()
1374 spin_lock_bh(&chan->desc_lock); in fsldma_resume_early()
1375 mode = chan->regs_save.mr in fsldma_resume_early()
1377 set_mr(chan, mode); in fsldma_resume_early()
1378 chan->pm_state = RUNNING; in fsldma_resume_early()
1379 spin_unlock_bh(&chan->desc_lock); in fsldma_resume_early()
1392 { .compatible = "fsl,elo3-dma", },
1393 { .compatible = "fsl,eloplus-dma", },
1394 { .compatible = "fsl,elo-dma", },
1401 .name = "fsl-elo-dma",
1411 /*----------------------------------------------------------------------------*/
1413 /*----------------------------------------------------------------------------*/