Lines Matching +full:dram +full:- +full:controller
2 * AMD64 class Memory Controller kernel module
5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc.
56 * is within a range affected by memory hoisting. The DRAM Base
57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers
60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr
76 * memory controller for the node that the DramAddr is associated
77 * with. The memory controller then maps the InputAddr to a csrow.
83 * The memory controller for a given node uses its DRAM CS Base and
84 * DRAM CS Mask registers to map an InputAddr to a csrow. See
105 * PCI-defined configuration space registers
131 * Function 1 - Address Map
147 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3))
148 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
149 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7))
152 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
153 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
154 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
157 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
169 * Function 2 - DRAM controller
178 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
179 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
201 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0))
202 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2))
204 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
206 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5))
207 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10))
218 * Function 3 - Misc Control
233 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
234 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
239 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */
317 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers
339 u32 ecc_ctrl; /* DRAM ECC Control reg */
358 u32 dclr0; /* DRAM Configuration Low DCT0 reg */
359 u32 dclr1; /* DRAM Configuration Low DCT1 reg */
360 u32 dchr0; /* DRAM Configuration High DCT0 reg */
361 u32 dchr1; /* DRAM Configuration High DCT1 reg */
365 u32 dhar; /* DRAM Hoist reg */
366 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */
367 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */
372 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
378 u32 dct_sel_lo; /* DRAM Controller Select Low */
379 u32 dct_sel_hi; /* DRAM Controller Select High */
380 u32 online_spare; /* On-Line spare Reg */
396 ERR_NODE = -1,
397 ERR_CSROW = -2,
398 ERR_CHANNEL = -3,
399 ERR_SYND = -4,
400 ERR_NORM_ADDR = -5,
421 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; in get_dram_base()
426 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; in get_dram_base()
431 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; in get_dram_limit()
436 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; in get_dram_limit()
446 if (pvt->fam == 0x15 && pvt->model >= 0x30) in dct_sel_interleave_addr()
447 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | in dct_sel_interleave_addr()
448 ((pvt->dct_sel_lo >> 6) & 0x3); in dct_sel_interleave_addr()
450 return ((pvt)->dct_sel_lo >> 6) & 0x3; in dct_sel_interleave_addr()
453 * per-node ECC settings descriptor
523 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dram_intlv_en()
525 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); in dram_intlv_en()
528 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; in dram_intlv_en()
533 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dhar_valid()
535 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); in dhar_valid()
538 return (pvt)->dhar & BIT(0); in dhar_valid()
543 if (pvt->fam == 0x15 && pvt->model >= 0x30) { in dct_sel_baseaddr()
545 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); in dct_sel_baseaddr()
548 return (pvt)->dct_sel_lo & 0xFFFFF800; in dct_sel_baseaddr()