Lines Matching +full:gpio +full:- +full:bank
2 * Broadcom Kona GPIO Driver
4 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
5 * Copyright (C) 2012-2014 Broadcom Corporation
20 #include <linux/gpio/driver.h>
30 #define GPIO_BANK(gpio) ((gpio) >> 5) argument
31 #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) argument
33 /* There is a GPIO control register for each GPIO */
34 #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) argument
36 /* The remaining registers are per GPIO bank */
37 #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) argument
38 #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) argument
39 #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) argument
40 #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) argument
41 #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) argument
42 #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) argument
43 #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) argument
44 #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) argument
91 unsigned gpio) in bcm_kona_gpio_lock_gpio() argument
95 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_lock_gpio()
97 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_lock_gpio()
99 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_lock_gpio()
100 val |= BIT(gpio); in bcm_kona_gpio_lock_gpio()
101 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_lock_gpio()
103 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_lock_gpio()
107 unsigned gpio) in bcm_kona_gpio_unlock_gpio() argument
111 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_unlock_gpio()
113 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_unlock_gpio()
115 val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); in bcm_kona_gpio_unlock_gpio()
116 val &= ~BIT(gpio); in bcm_kona_gpio_unlock_gpio()
117 bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); in bcm_kona_gpio_unlock_gpio()
119 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_unlock_gpio()
122 static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_get_dir() argument
125 void __iomem *reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get_dir()
128 val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; in bcm_kona_gpio_get_dir()
132 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) in bcm_kona_gpio_set() argument
136 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_set()
137 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_set()
142 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set()
143 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_set()
146 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) in bcm_kona_gpio_set()
156 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_set()
159 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_get() argument
163 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_get()
164 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_get()
169 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_get()
170 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_get()
172 if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN) in bcm_kona_gpio_get()
177 /* read the GPIO bank status */ in bcm_kona_gpio_get()
180 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_get()
186 static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_request() argument
190 bcm_kona_gpio_unlock_gpio(kona_gpio, gpio); in bcm_kona_gpio_request()
194 static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_free() argument
198 bcm_kona_gpio_lock_gpio(kona_gpio, gpio); in bcm_kona_gpio_free()
201 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_direction_input() argument
209 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_input()
210 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_input()
212 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_input()
215 writel(val, reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_input()
217 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_input()
223 unsigned gpio, int value) in bcm_kona_gpio_direction_output() argument
227 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_direction_output()
228 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_direction_output()
233 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_direction_output()
234 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_output()
236 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_output()
239 writel(val, reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_direction_output()
246 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_direction_output()
251 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) in bcm_kona_gpio_to_irq() argument
256 if (gpio >= kona_gpio->gpio_chip.ngpio) in bcm_kona_gpio_to_irq()
257 return -ENXIO; in bcm_kona_gpio_to_irq()
258 return irq_create_mapping(kona_gpio->irq_domain, gpio); in bcm_kona_gpio_to_irq()
261 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio, in bcm_kona_gpio_set_debounce() argument
270 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_set_debounce()
271 /* debounce must be 1-128ms (or 0) */ in bcm_kona_gpio_set_debounce()
273 dev_err(chip->parent, "Debounce value %u not in range\n", in bcm_kona_gpio_set_debounce()
275 return -EINVAL; in bcm_kona_gpio_set_debounce()
283 res = fls(debounce) - 1; in bcm_kona_gpio_set_debounce()
284 /* Check if MSB-1 is set (round up or down) */ in bcm_kona_gpio_set_debounce()
285 if (res > 0 && (debounce & BIT(res - 1))) in bcm_kona_gpio_set_debounce()
289 /* spin lock for read-modify-write of the GPIO register */ in bcm_kona_gpio_set_debounce()
290 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_set_debounce()
292 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_set_debounce()
303 writel(val, reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_set_debounce()
305 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_set_debounce()
310 static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio, in bcm_kona_gpio_set_config() argument
316 return -ENOTSUPP; in bcm_kona_gpio_set_config()
319 return bcm_kona_gpio_set_debounce(chip, gpio, debounce); in bcm_kona_gpio_set_config()
323 .label = "bcm-kona-gpio",
341 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_ack() local
342 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_irq_ack()
343 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_irq_ack()
348 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_ack()
349 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_ack()
355 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_ack()
362 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_mask() local
363 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_irq_mask()
364 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_irq_mask()
369 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_mask()
370 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_mask()
375 gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_mask()
377 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_mask()
384 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_unmask() local
385 int bank_id = GPIO_BANK(gpio); in bcm_kona_gpio_irq_unmask()
386 int bit = GPIO_BIT(gpio); in bcm_kona_gpio_irq_unmask()
391 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_unmask()
392 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_unmask()
397 gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio); in bcm_kona_gpio_irq_unmask()
399 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_unmask()
406 unsigned gpio = d->hwirq; in bcm_kona_gpio_irq_set_type() local
412 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_irq_set_type()
428 /* BCM GPIO doesn't support level triggering */ in bcm_kona_gpio_irq_set_type()
430 dev_err(kona_gpio->gpio_chip.parent, in bcm_kona_gpio_irq_set_type()
431 "Invalid BCM GPIO irq type 0x%x\n", type); in bcm_kona_gpio_irq_set_type()
432 return -EINVAL; in bcm_kona_gpio_irq_set_type()
435 raw_spin_lock_irqsave(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_set_type()
437 val = readl(reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_irq_set_type()
440 writel(val, reg_base + GPIO_CONTROL(gpio)); in bcm_kona_gpio_irq_set_type()
442 raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); in bcm_kona_gpio_irq_set_type()
452 struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc); in bcm_kona_gpio_irq_handler() local
458 * For bank interrupts, we can't use chip_data to store the kona_gpio in bcm_kona_gpio_irq_handler()
460 * our pointer from the bank structure. in bcm_kona_gpio_irq_handler()
462 reg_base = bank->kona_gpio->reg_base; in bcm_kona_gpio_irq_handler()
463 bank_id = bank->id; in bcm_kona_gpio_irq_handler()
470 irq_find_mapping(bank->kona_gpio->irq_domain, in bcm_kona_gpio_irq_handler()
490 return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq); in bcm_kona_gpio_irq_reqres()
497 gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq); in bcm_kona_gpio_irq_relres()
501 .name = "bcm-kona-gpio",
511 { .compatible = "brcm,kona-gpio" },
516 * This lock class tells lockdep that GPIO irqs are in a different
527 ret = irq_set_chip_data(irq, d->host_data); in bcm_kona_gpio_irq_map()
554 reg_base = kona_gpio->reg_base; in bcm_kona_gpio_reset()
556 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_reset()
557 /* Unlock the entire bank first */ in bcm_kona_gpio_reset()
561 /* Now re-lock the bank */ in bcm_kona_gpio_reset()
568 struct device *dev = &pdev->dev; in bcm_kona_gpio_probe()
570 struct bcm_kona_gpio_bank *bank; in bcm_kona_gpio_probe() local
578 dev_err(dev, "Failed to find gpio controller\n"); in bcm_kona_gpio_probe()
579 return -ENODEV; in bcm_kona_gpio_probe()
584 return -ENOMEM; in bcm_kona_gpio_probe()
586 kona_gpio->gpio_chip = template_chip; in bcm_kona_gpio_probe()
587 chip = &kona_gpio->gpio_chip; in bcm_kona_gpio_probe()
590 dev_err(dev, "Couldn't determine # GPIO banks\n"); in bcm_kona_gpio_probe()
591 return -ENOENT; in bcm_kona_gpio_probe()
593 return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n"); in bcm_kona_gpio_probe()
595 kona_gpio->num_bank = ret; in bcm_kona_gpio_probe()
597 if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { in bcm_kona_gpio_probe()
598 dev_err(dev, "Too many GPIO banks configured (max=%d)\n", in bcm_kona_gpio_probe()
600 return -ENXIO; in bcm_kona_gpio_probe()
602 kona_gpio->banks = devm_kcalloc(dev, in bcm_kona_gpio_probe()
603 kona_gpio->num_bank, in bcm_kona_gpio_probe()
604 sizeof(*kona_gpio->banks), in bcm_kona_gpio_probe()
606 if (!kona_gpio->banks) in bcm_kona_gpio_probe()
607 return -ENOMEM; in bcm_kona_gpio_probe()
609 kona_gpio->pdev = pdev; in bcm_kona_gpio_probe()
611 chip->of_node = dev->of_node; in bcm_kona_gpio_probe()
612 chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; in bcm_kona_gpio_probe()
614 kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node, in bcm_kona_gpio_probe()
615 chip->ngpio, in bcm_kona_gpio_probe()
618 if (!kona_gpio->irq_domain) { in bcm_kona_gpio_probe()
620 return -ENXIO; in bcm_kona_gpio_probe()
623 kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0); in bcm_kona_gpio_probe()
624 if (IS_ERR(kona_gpio->reg_base)) { in bcm_kona_gpio_probe()
625 ret = PTR_ERR(kona_gpio->reg_base); in bcm_kona_gpio_probe()
629 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_probe()
630 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()
631 bank->id = i; in bcm_kona_gpio_probe()
632 bank->irq = platform_get_irq(pdev, i); in bcm_kona_gpio_probe()
633 bank->kona_gpio = kona_gpio; in bcm_kona_gpio_probe()
634 if (bank->irq < 0) { in bcm_kona_gpio_probe()
635 dev_err(dev, "Couldn't get IRQ for bank %d", i); in bcm_kona_gpio_probe()
636 ret = -ENOENT; in bcm_kona_gpio_probe()
641 dev_info(&pdev->dev, "Setting up Kona GPIO\n"); in bcm_kona_gpio_probe()
647 dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); in bcm_kona_gpio_probe()
650 for (i = 0; i < kona_gpio->num_bank; i++) { in bcm_kona_gpio_probe()
651 bank = &kona_gpio->banks[i]; in bcm_kona_gpio_probe()
652 irq_set_chained_handler_and_data(bank->irq, in bcm_kona_gpio_probe()
654 bank); in bcm_kona_gpio_probe()
657 raw_spin_lock_init(&kona_gpio->lock); in bcm_kona_gpio_probe()
662 irq_domain_remove(kona_gpio->irq_domain); in bcm_kona_gpio_probe()
669 .name = "bcm-kona-gpio",